Input Pin Level Latching to Cut Leakage in Floating-State Detection

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Solution Overview

Problem

Conventional input circuits for integrated circuits generate leakage current when determining the state of an input pin, particularly when the pin is in a floating state, as they rely on resistors to pull the pin's level high or low, leading to inefficiencies and potential noise interference.

Innovation Solution

The proposed input circuit employs a level-determining unit and an output unit, with enable signals controlling the determination and latching of voltage levels, using switches and resistors to minimize leakage current and prevent noise interference by switching paths during different periods, and includes an analog-digital converting unit and latch module to accurately determine input states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a resistor is used to pull the input pin level high or low when the pin is in a floating state, then the input state can be determined, but leakage current is generated on the path formed by the resistor between the input pin and the ground

Engineering Contradiction:
Improveinput state determinationVSAvoidleakage current
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the resistor connection dynamic rather than static. A switch controlled by a control signal connects the resistor to the input pin only when needed (when the pin is in floating state), and disconnects it when the pin is in high or low logic state. This dynamic switching eliminates continuous leakage current while maintaining the ability to determine input states when required.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action through periodic sampling of the input pin state. The control signal periodically activates the switch to sample the input pin level, determines its state, and then deactivates the switch. This periodic sampling approach allows the system to determine input states without maintaining continuous resistor connections that would generate constant leakage current.

Inventive Principle:
Principle #19Periodic action

2Measurement precision

If a resistor is used to pull the input pin level, then the floating state can be determined, but noise interference may occur

Engineering Contradiction:
Improvefloating state detectionVSAvoidnoise interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The dynamic switching mechanism connects the resistor to the input pin only during brief sampling periods when the control signal is active. During normal operation (when the pin is in defined logic states), the switch disconnects the resistor, preventing it from introducing noise into the signal path. This dynamic connection minimizes noise interference while maintaining floating state detection capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses rapid periodic sampling to quickly detect the floating state and then immediately disconnects the resistor. This rushing through the detection process minimizes the time the resistor is connected to the input pin, thereby reducing the window for noise interference while still achieving accurate floating state detection.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS7609094B2Input circuits and methods thereof
Publication Date: 2009.10.27 MEDIATEK INC
  • US7609094B2 patent drawing
  • US7609094B2 patent drawing
  • US7609094B2 patent drawing

AI summary

An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined voltage level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined voltage level of the input signal according to a second enable signal and outputs the input signal with the determined voltage level at the output terminal to serve as the output signal.