Digital Clock Duty Cycle Correction with LPF Feedback Measurement
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Solution Overview
Problem
Existing technologies face challenges in monitoring high frequency signals without substantial loss of duty cycle information due to bandwidth limitations in test equipment, leading to difficulties in accurately measuring and correcting duty cycles in microprocessor operations.
Innovation Solution
A digital circuit employing a plurality of Low Pass Filters (LPFs) and a correction circuit that compares outputs to restore and correct duty cycle information, using dividers and counters to increment or decrement the duty cycle of the clock signal, ensuring minimal loss of duty cycle data during frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If frequency division is used to monitor high frequency signals, then the signals can be easily characterized in test setup, but duty cycle information is lost
Solution Approach 1:
The patent segments the monitoring function into two parallel paths: one path performs frequency division for ease of monitoring, while the other path uses Low Pass Filters to extract and preserve duty cycle information. Both paths operate independently but feed into a unified measurement system, allowing the system to benefit from frequency division while retaining duty cycle data through the filter-based extraction method.
2Measurement precision
If test equipment bandwidth is increased to directly monitor high frequency signals, then duty cycle information is preserved, but equipment complexity and cost increase
Solution Approach 1:
The patent introduces Low Pass Filters as intermediary elements that mediate between the high frequency signal source and the measurement system. These filters extract duty cycle information by passing the signal through multiple filtering stages, converting the high frequency duty cycle variations into measurable low frequency voltage variations without requiring the test equipment to have high bandwidth capabilities.
3Speed
If pulse width is reduced to increase operating frequency, then microprocessor speed increases, but duty cycle control becomes critical
Solution Approach 1:
The patent implements a feedback mechanism where the Low Pass Filters continuously monitor the duty cycle of the clock signal, and the measured duty cycle information is fed back to the control system. This feedback loop enables real-time duty cycle control and correction, allowing the system to maintain precise duty cycle control even at high operating frequencies where pulse widths are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively measures and corrects duty cycles with high accuracy, maintaining duty cycle information integrity, achieving ±1% accuracy and robustness against process-induced mismatches, suitable for advanced digital CMOS technology applications.
Implementation Method 1
A plurality of Low Pass Filters (LPFs) is employed. These LPFs output signals that are proportional to the duty cycles of input signals
Implementation Method 2
a comparator compares outputs of the LPFs to output a feedback signal to the correction circuit
Data Source
AI summary
A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.