Local Skew Detecting Circuit for Memory Timing Compensation
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in accurately monitoring and compensating for local skew, which causes variations in critical dimension (CD) and threshold voltage (Vt) across different locations on a chip, leading to differing operating parameters for circuits of the same function.
Innovation Solution
A local skew detecting circuit is introduced, comprising a reference delay block and timing detecting blocks that generate and compare delay signals to detect enable timing orders, enabling the generation of detection signals that highlight characteristic changes across chip locations, allowing for compensation in setup/hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If local skew detection is implemented to monitor characteristic changes at different chip locations, then manufacturing precision and reliability are improved, but device complexity increases due to additional detection circuits and timing blocks
Solution Approach 1:
The detection circuit is divided into multiple independent timing detecting blocks, each responsible for a specific location (center, right, left) on the chip. Each block contains delay units and detection units that operate independently to monitor local skew characteristics at their respective locations, enabling distributed measurement without requiring a monolithic complex circuit
Solution Approach 2:
Delay units are introduced as intermediary components between the test signal source and the detection units. These delay units generate delayed versions of the test signal (e.g., TDLY1, TDLY2) that serve as reference signals for comparison, enabling the detection of timing skew without directly measuring the raw signals
2Measurement precision
If delay units and timing detecting blocks are added to detect local skew, then measurement precision is improved, but the area of the chip increases
Solution Approach 1:
The detection circuit implements local quality by dedicating specific detection resources to specific locations on the chip. The center timing detecting block monitors the center location, while right and left timing detecting blocks monitor their respective locations. This localized approach allows precise measurement at each location without requiring full-chip coverage from every detection element
Solution Approach 2:
The circuit uses a selective approach where only certain critical locations (center, right, left) are monitored with full detection blocks, while other areas are inferred or monitored with reduced resources. This partial action approach provides sufficient measurement precision for quality control without implementing detection across every possible location
Data Source
AI summary
A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.