Adaptive ADC Resolution in Digital Equalizers for Lower Receiver Power
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Solution Overview
Problem
Existing digital data communication systems face inefficiencies in power consumption due to the need for full-resolution processing in receivers, even when channels have low attenuation, distortion, and noise, leading to unnecessary power usage.
Innovation Solution
Implementing a variable resolution analog-to-digital converter (ADC) and processing logic that dynamically adjusts the number of bits based on channel attenuation, reducing power consumption by disabling unused circuitry and reducing the number of bits processed in low-loss channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-resolution processing is used in receivers, then measurement precision and reliability are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic resolution adjustment where the ADC and processing logic switch between full-resolution mode and reduced-resolution mode based on channel conditions. When channel attenuation is low and signal quality is good, the system reduces the number of bits processed by the ADC and disables portions of the processing logic, thereby reducing power consumption while maintaining adequate measurement precision. Conversely, when channel conditions deteriorate, the system automatically increases resolution to maintain reliability.
Solution Approach 2:
The system changes the resolution parameter of the ADC dynamically based on channel attenuation measurements. By adjusting the number of bits output by the ADC and the processing depth of the logic circuitry according to actual channel conditions, the system optimizes the balance between measurement precision and power consumption, avoiding unnecessary high-resolution processing when it is not required by the channel state.
2Reliability
If full-resolution processing is used in receivers, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic resolution adjustment where the ADC and processing logic switch between full-resolution mode and reduced-resolution mode based on channel conditions. When channel attenuation is low and signal quality is good, the system reduces the number of bits processed by the ADC and disables portions of the processing logic, thereby reducing power consumption while maintaining adequate measurement precision. Conversely, when channel conditions deteriorate, the system automatically increases resolution to maintain reliability.
Solution Approach 2:
The system uses feedback from channel attenuation measurements to control the ADC resolution and processing logic activation. The receiver monitors channel conditions and adjusts its processing resolution accordingly, creating a closed-loop system that maintains reliability by increasing resolution when channel conditions worsen while reducing power consumption when conditions are good.
Data Source
AI summary
A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.