Power Saving Provisions TRIZ Cases

Extending the DAC feedback clock during sampling cuts integrator power use while preserving low-noise current integration.

A feedback-subtraction ADC path keeps the microphone amplifier out of saturation, cutting harmonic distortion and improving SNDR and SFDR.

Shadow capacitor switching keeps RF DAC output impedance more constant, cutting code-dependent loading, distortion, and ACLR.

Line and load voltage feedback adjusts switching transitions to cut heat, reduce EMI, and improve power efficiency in lighting circuits.

A low-power audio activity detector uses PWM and clock time encoding to wake speech processing early and reduce missed audio.

Integrating buffers give time-interleaved ADC front ends linear settling, cutting power demand while easing bandwidth limits for high-speed sampling.

A single track-and-hold circuit uses dither injection to remove interleaved ADC timing mismatch, calibrate gain and offset, and cut power.

A dual-mode ADC cuts sensor power use by comparing against a threshold and only running full digital conversion when needed.

Current-mode DAC multipliers cut power and cost for edge AI MACs while preserving digital interfacing in mainstream CMOS.

By extending the comparison signal duration, this ADC achieves high resolution with a slower clock and lower power consumption.

Asynchronous multi-stage current-mode ADCs cut clock noise, glitch, power use, and die area while preserving accuracy at low supply voltage.

Shared bootstrap capacitors and switches cut gate count, clock routing, and area in time-interleaved ADC sample-and-hold circuits.

A latch-integrated pre-amplifier and capacitive level shifting cut comparator power and area while preserving fast ADC signal acquisition.

Extending the feedback clock only during sampling cuts integrator power use while preserving low noise in delta-sigma current integration.

By charging a capacitor during conversion, the ADC powers the DSP directly, reducing PMIC loss, heat, and chip area.

Free-running phase signals keep TDC sampling asynchronous, suppressing delay-variation linearity loss while sharing the system clock.

Series-switched capacitors create precise minute dither voltage in a ΔΣ ADC, reducing variation sensitivity, noise impact, and trimming needs.

Receiver ADC and equalization logic cut valid-bit processing on low-loss channels, reducing power while preserving signal reliability.

A low-resolution ADC monitors signal changes and activates high-resolution conversion only when needed, cutting power use and bandwidth load.

Varying delay times across TDC stages preserves wide dynamic range while cutting stage count, chip area, and power use.

Multiple signal samples are averaged through capacitor charge redistribution to filter analog noise without sacrificing image definition.

A ramp-plus-residue ADC cuts comparator count, conversion time, and power while preserving high-resolution digital accuracy.

Adjustable resistor and capacitor banks let a pipelined ADC match wide input ranges on the fly while avoiding extra gain-stage power and noise.

Dedicated on-chip reference capacitors speed SAR ADC bit decisions while making bit weights signal-independent for easier calibration.

Signal amplitude detection disables unneeded DAC current modules and switches bias states to cut power while limiting jitter and nonlinearity.

A single track-and-hold circuit uses dither-based calibration to cut interleaved ADC mismatch, power use, and nonlinearity.

An initial half-ramp comparison predecides one bit, cutting ADC clock demand to enable faster CMOS image sensor conversion with lower power.

Linear combination and inversion of multiple sensor signals avoids time-sharing losses, improving SNR while handling varied sensor types.

A timing amplifier extends the CDS comparison signal so an ADC can keep high resolution with a slower clock and lower power use.

Multiple ADC paths with different gain and noise floors are switched by input amplitude to cut power use while preserving signal fidelity.

Feedback-based gain correction compensates DAC mismatches inside an ADC path, improving analog-to-digital conversion accuracy.

A reservoir capacitor and switched references let a SAR ADC handle varying common-mode voltage with fewer nonlinear errors, less noise, and no extra circuitry.

By reusing higher bits from the previous output and converting only changing lower bits, this SAR ADC cuts clock cycles and power.

Threshold-based mode switching lets an ADC skip unnecessary conversions, cutting power use without sacrificing data rate.

Stops sequential bit generation when the signal falls outside a target range, cutting ADC power use without lowering sampling rate.

Independent electrode actuation linearizes Mach-Zehnder optical DAC modulation, improving dynamic range and resolution at high speed.

An adaptive reference clock and event-driven TDC cut 3D imager power use while preserving photon timing precision for long-range sensing.

Repeated DAC bit trials and weighted averaging suppress ADC noise while preserving signal level, SNR, power, and die area.

Offset injection across ADC comparators staggers inversion timing to cut power spikes, supply noise, jitter, and linearity errors.

Capacitor array reconfiguration extends SAR ADC dynamic range without increasing reference voltage, power consumption, or circuit complexity.

Asynchronous SAR sub-conversions with completion feedback help time-interleaved ADCs balance speed, accuracy, and power.

Conversion-time feedback adjusts SAR ADC supply voltage to lower power use without extending conversion time or causing errors.

Dual reference sweeps and averaged limited-range conversions cut ADC noise while preserving conversion speed and power in sensor readout.

Passive SAT filtering feeds prior-cycle residue back into an oversampling SAR ADC to achieve higher-order noise shaping with lower power and area.

Dynamic power switching steers DAC current to a lower secondary supply during inactive phases, cutting power waste without losing gain.

Weighted averaging across high- and low-gain ADC paths cuts switching artifacts while extending dynamic range in signal processing.

State-count-based comparator stopping improves SAR ADC accuracy under noise while reducing power use during bit determination.

Multiple Mach-Zehnder electrodes and bit mapping linearize optical DAC output, cutting distortion while extending dynamic range.