Embedded PGA Pipelined ADC for Wide Input Range at Low Supply
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Solution Overview
Problem
In system-on-a-chip (SoC) integrated circuits, the reduction of power supply voltage complicates analog circuitry design, particularly for Analog-to-Digital Converters (ADCs), as they need to operate on lower digital supplies while maintaining performance, leading to issues with input range mismatches and increased noise or power consumption when additional stages are added to reduce signal range.
Innovation Solution
Incorporating a Programmable Gain Amplifier (PGA) into pipelined ADCs, allowing for adjustable gain stages and sampling capacitor ratios to reduce the input range without adding extra power-consuming stages, thereby optimizing system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ADC operates on lower digital supply voltage, then power consumption is reduced, but input full-scale range must be reduced
Solution Approach 1:
The patent implements a programmable gain amplifier (PGA) with adjustable gain stages that can be dynamically configured to match different input signal ranges. The PGA allows the ADC to adapt its effective input range by applying appropriate gain values, enabling the system to maintain full-scale range capability while operating from lower digital supply voltages.
2Adaptability or versatility
If an extra gain amplifier stage is added before ADC to reduce signal range, then input range matching is improved, but noise increases due to resistor thermal noise
Solution Approach 1:
The patent merges the PGA functionality directly into the ADC architecture, integrating the gain control stages within the existing converter structure. This integration allows for coordinated operation of the gain stages with the ADC's sampling and conversion processes, reducing the need for separate external amplifier stages and their associated noise-generating resistors.
3Adaptability or versatility
If Sample and Hold stage is added before ADC to reduce signal range, then input range matching is improved, but linearity degrades due to large sampling capacitor loading
Solution Approach 1:
The patent employs dynamic sampling capacitor configurations where the capacitor values can be adjusted based on the selected gain stage. This dynamic adjustment optimizes the capacitive loading conditions for each gain setting, maintaining linearity across different input range configurations by preventing excessive loading effects.
4Adaptability or versatility
If extra gain amplifier or Sample and Hold stage is added, then input range is reduced, but power consumption increases
Solution Approach 1:
The patent combines the PGA functionality with the existing ADC operational amplifiers and circuitry, reusing existing components to provide gain control. This merging approach eliminates the need for completely separate amplifier stages, thereby reducing the additional power consumption that would result from fully independent extra stages.
Data Source
AI summary
A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.