Current Integration Circuit With Extended Feedback Clock Sampling
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Solution Overview
Problem
Current integration circuits in delta-sigma converters face challenges with high power consumption and noise due to the pulsed nature of feedback clock signals, which limits the gain-bandwidth product and increases settling time, while attempts to reduce power consumption often compromise noise performance.
Innovation Solution
The method involves extending the feedback clock period during sampling and reducing the gain-bandwidth product of the operational transconductance amplifier, allowing for increased settling time and power savings by elevating electric power only during sampling, and using a parallel connection of an operational transconductance amplifier and an integration capacitor with a digital-to-analog converter generating feedback pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the feedback clock period is extended during sampling, then power consumption is reduced, but settling time increases
Solution Approach 1:
The feedback clock period is dynamically adjusted based on the operational phase: during integration phases, the period is shorter to ensure proper settling, while during sampling phases, the period is extended to reduce power consumption. This dynamic timing adjustment allows the system to optimize both settling performance and energy efficiency at different operational moments.
Solution Approach 2:
The system employs periodic feedback pulses rather than continuous feedback, with the feedback clock period being extended during sampling intervals. This periodic action with variable period length allows the integrator to consume less power during sampling while maintaining adequate settling during integration phases.
2Use of energy by moving object
If the gain-bandwidth product is reduced, then power consumption is reduced, but noise performance deteriorates
Solution Approach 1:
The gain-bandwidth product of the operational transconductance amplifier is dynamically adjusted: reduced during sampling phases to minimize power consumption, and increased during integration phases to maintain low noise performance. This dynamic parameter adjustment resolves the contradiction between power efficiency and noise performance.
Solution Approach 2:
The system changes the operating parameters of the OTA (specifically the gain-bandwidth product) based on the operational phase. By lowering the GBW during sampling when noise integration is minimal, and restoring it during integration when noise filtering is critical, the system achieves both low power consumption and acceptable noise performance.
3Use of energy by moving object
If the feedback clock period is extended, then power consumption is reduced, but the noise filtering capability is reduced
Solution Approach 1:
The extended feedback clock period is applied periodically only during sampling phases rather than continuously. During integration phases, the shorter period maintains effective noise filtering. This periodic application of extended timing allows power reduction without permanently compromising noise filtering capability.
Solution Approach 2:
The feedback clock period is dynamically switched between two values: a shorter period during integration for optimal noise filtering, and an extended period during sampling for power reduction. This dynamic switching allows the system to achieve both low power consumption and effective noise filtering at different operational moments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by a factor of N, particularly by half, while maintaining low noise performance, especially for lower signal ranges, and allows for higher signal-to-noise ratio without compromising the output noise.
Implementation Method 1
The input current I in is integrated on the integration capacitor C int, thus leading to a growing output integrated voltage V out_int
Implementation Method 2
an operational transconductance amplifier (OTA), the input of which is connected to the positive input of the OTA and the output of which is connected to the negative input of the OTA
Data Source
Figure 1~1c
Figure 2~2b
Figure 3~3b
AI summary
An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).