Asynchronous Current-Mode ADCs With Low Glitch and Low Power
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs), particularly current-mode ADCs, face challenges in operating with low voltage power supplies, experiencing glitches, and requiring high power consumption, large die size, and complex circuitry, which limits their performance and accuracy in low-power applications.
Innovation Solution
The development of a current-mode signal conditioning system with multi-staged current-mode analog-to-digital converters (iADCs) that operate asynchronously, eliminating the need for clocks and passive components, and utilizing scaled reference current sources to condition current signals, allowing for zero-to-full scale input handling with low voltage power supplies and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage-mode ADCs with switch-capacitor techniques are used, then low offset and low noise performance is achieved, but the input voltage signal range is limited to the maximum available power supply voltage
Solution Approach 1:
The patent transitions from voltage-mode to current-mode operation, changing the fundamental operating parameter of the ADC. This allows the input signal range to be determined by current levels rather than voltage supply limits, enabling operation with low voltage power supplies while maintaining full-scale input capability through current signal processing.
2Use of energy by moving object
If switch-capacitor techniques are used to pump-up internal power supply voltage, then low voltage supply operation is enabled, but circuit complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the switch-capacitor voltage pumping circuitry from the ADC design. By adopting current-mode operation, the need for complex voltage multiplication circuits is removed, simplifying the overall architecture while enabling low-voltage operation through direct current signal processing.
Solution Approach 2:
The patent replaces the mechanical/electrical voltage pumping mechanism with a current-mode signal processing approach. Instead of using switch-capacitor networks to boost internal voltages, the design uses current mirrors and transconductance amplifiers that naturally operate from low voltage supplies, substituting a simpler electrical mechanism for the complex voltage multiplication system.
3Stability of the object's composition
If voltage-mode ADCs are used, then sample and hold capability is provided, but transient response is impeded and input-to-output glitch rejection is degraded
Solution Approach 1:
The patent substitutes the voltage-mode sample-and-hold mechanism with a current-mode equivalent. Current-mode circuits inherently provide faster transient response because current changes can occur more rapidly than voltage changes, while still maintaining signal stability through current mirrors and buffered current sources that replicate the sample-and-hold function.
4Extent of automation
If free running clocks are used for voltage-mode ADCs, then clocked operation is achieved, but dynamic power consumption increases and digital system noise is raised
Solution Approach 1:
The patent replaces continuous free-running clock operation with periodic sampling pulses in the current-mode architecture. This allows the ADC to operate asynchronously or with minimal clocking, reducing dynamic power consumption associated with continuous clock distribution and switching activity while maintaining the necessary timing control for conversion operations.
5Speed
If conventional flash-based current-mode ADCs are used, then fast conversion is achieved, but power consumption and die area increase exponentially with resolution
Solution Approach 1:
The patent segments the conversion process into multiple stages, using a tree-structured architecture where successive refinement of the digital output occurs through hierarchical processing. This segmentation allows high-speed conversion to be achieved with manageable power consumption and die area at each stage, avoiding the exponential growth associated with single-stage flash converters.
Solution Approach 2:
The patent transitions from a single-dimensional flash converter approach to a multi-dimensional tree-structured architecture. By organizing the conversion process across multiple hierarchical levels and parallel processing paths, the design achieves high speed while controlling resource consumption through distributed processing rather than centralized high-power operation.
Data Source
AI summary
Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.