Current Integration Circuit With Extended DAC Sampling Period
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Solution Overview
Problem
Current integration circuits in delta-sigma analog-to-digital converters face challenges with output noise and power consumption due to the pulsed nature of feedback clock signals, which limits settling speed and increases noise filtering, and existing solutions like smoothing filters can cause instability.
Innovation Solution
The method involves extending the feedback clock period during sampling, reducing the gain-bandwidth product of the operational transconductance amplifier, and using a range check based on feedback pulses to manage output integrated voltage, allowing for reduced power consumption and improved noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pulsed feedback is used through DAC during feedback clock period, then feedback control is achieved, but settling time increases and power consumption increases significantly
Solution Approach 1:
The patent applies periodic action by using a feedback clock signal to periodically enable the DAC and switch elements. The feedback clock has a period Tclk_DAC that is synchronized with the integration process, allowing the system to achieve settling during specific time windows while consuming power only during active feedback periods rather than continuously
Solution Approach 2:
The patent implements dynamics by making the feedback clock period Tclk_DAC variable and adaptive. The feedback clock period is adjusted based on the integration capacitor voltage level and input current magnitude, allowing the system to optimize between settling time and power consumption dynamically rather than using fixed parameters
2Productivity
If pulsed feedback clock signal is used, then feedback timing is controlled, but output noise increases due to insufficient settling time
Solution Approach 1:
The patent applies preliminary action by ensuring the DAC and switch elements are enabled early in the feedback clock period Tclk_DAC, before the critical measurement phase. This preliminary enabling allows the feedback voltage to settle to its final value well before sampling occurs, ensuring noise-free operation
Solution Approach 2:
The patent uses feedback by continuously monitoring the integration capacitor voltage Vout_int and using this information to control the DAC output current. The feedback loop adjusts the DAC current to maintain the integration voltage within acceptable bounds while ensuring sufficient settling time before sampling
3Use of energy by stationary object
If transconductance gm is reduced to lower power consumption, then power consumption decreases, but noise performance deteriorates
Solution Approach 1:
The patent implements dynamics by making the transconductance gm variable rather than fixed. The transconductance is adjusted dynamically based on the operating conditions, input current magnitude, and feedback clock period, allowing the system to optimize the noise-power tradeoff in real-time rather than being constrained by fixed device parameters
Solution Approach 2:
The patent applies parameter changes by modifying the feedback clock period Tclk_DAC and transconductance gm as system parameters. By changing these parameters adaptively based on operating conditions, the system can maintain low noise performance while reducing power consumption, as the noise is inversely proportional to the feedback clock period
4Object-affected harmful factors
If smoothing filter is added after DAC, then output noise is reduced, but system stability deteriorates in higher order feedback paths
Solution Approach 1:
The patent applies preliminary action by ensuring the feedback voltage settles to its final value during the feedback clock period Tclk_DAC before the sampling phase begins. This preliminary settling eliminates the need for additional smoothing filters that would compromise stability, as the noise is already minimized by the timing of the periodic feedback action
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by a factor of N, particularly by half, while maintaining low noise performance, especially for lower signal ranges, and avoids instability issues associated with higher order feedback paths.
Implementation Method 1
The input current Iin is integrated on the integration capacitor Cint, thus leading to a growing output integrated voltage Vout_int
Implementation Method 2
Pulsed feedback is effected by a digital-to-analog converter (DAC), which may be a switched capacitor digital-to-analog converter
Data Source
AI summary
An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).