ADC Timing Amplifier for High Resolution at Lower Clock Power
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Solution Overview
Problem
Analog to digital converters (ADCs) face a challenge in reducing power consumption while maintaining high resolution, as they typically require high-speed clock signals to support increased resolution, leading to increased power usage.
Innovation Solution
The ADC circuit incorporates a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, a timing amplifier that extends the active time of the comparison signal 'N' times, and a counter that generates a digital signal using a slower clock signal, allowing for equivalent resolution with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed clock signal is used to increase ADC resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing correlated double sampling to pre-process the analog signal and generate a comparison signal before the main conversion process. This preliminary processing extends the active time of the comparison signal, allowing the counter to use a slower clock signal while still achieving the required resolution, thus reducing power consumption without sacrificing measurement precision
Solution Approach 2:
The patent implements dynamics by making the active time of the comparison signal variable through the timing amplifier extension mechanism. The comparison signal's active time is dynamically extended to be longer than the original comparison period, enabling the system to operate with lower clock frequencies while maintaining the necessary counting accuracy for high-resolution conversion
Data Source
AI summary
An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.