ADC Noise Reduction Using Redundant DAC Bit Trials
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Solution Overview
Problem
Analog-to-digital converter (ADC) circuits face challenges in achieving high accuracy while minimizing power consumption and die area, particularly in precision measurement systems, as existing calibration methods require increased power, time, and additional circuitry, and noise reduction techniques often compromise signal-to-noise ratio (SNR) due to ADC non-linearity.
Innovation Solution
The proposed solution involves utilizing a digital-to-analog converter (DAC) circuit with redundant unit elements or non-binary weighted capacitors for repeated bit trials, averaging the data from these trials to suppress noise, thereby reusing the existing DAC circuit for noise reduction and improving SNR without increasing power or die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing calibration methods are used to improve ADC accuracy, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The DAC circuit serves dual purposes: its original function and noise reduction through repeated bit trials. By reusing the same hardware resources for multiple functions, the system achieves accuracy improvement without additional power-consuming calibration circuits
Solution Approach 2:
The patent performs M bit-trials where M exceeds the minimum N bits required for resolution. This excessive action (M > N) allows noise averaging while the weighted averaging process ensures the additional trials contribute efficiently to both accuracy and noise reduction
2Measurement precision
If existing calibration methods are used to improve ADC accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The DAC circuit is designed to perform its primary conversion function while simultaneously executing noise reduction through repeated bit trials. This multi-functionality eliminates the need for separate calibration circuits, maintaining simplicity while improving accuracy
Solution Approach 2:
The patent combines the calibration function and noise reduction function into the existing DAC circuit operations. By merging these functions into a single unified process using the same hardware, device complexity is avoided while achieving improved measurement precision
3Measurement precision
If noise reduction techniques are applied to improve SNR, then signal-to-noise ratio is improved, but processing time increases
Solution Approach 1:
The patent performs M bit-trials where M is greater than the minimum N bits needed, enabling noise averaging. The weighted averaging process then efficiently processes these trials to achieve noise reduction with optimized processing time
Solution Approach 2:
The patent changes the parameter from simple binary weighting to weighted averaging with different weights for different bit positions. This parameter change allows the system to process M trials more efficiently, reducing the time penalty associated with repeated trials by giving higher weight to more reliable bit measurements
4Measurement precision
If repeated bit trials are performed to reduce noise, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The DAC circuit performs both its primary conversion function and noise reduction through repeated bit trials using the same hardware resources. This multi-functionality allows noise reduction without requiring additional power-consuming dedicated noise reduction circuits
Solution Approach 2:
The system uses its own existing DAC circuit to perform noise reduction through repeated trials, rather than relying on external or additional power-consuming noise reduction mechanisms. The circuit serves itself for both conversion and noise suppression
Data Source
AI summary
Improvements in analog-to-digital converter (ADC) circuit accuracy are described that can utilize a digital-to-analog converter (DAC) circuit with one or more redundant unit elements, or one or more bits redundancy or non-binary weighted capacitors, and can reuse the existing DAC circuit for noise reduction to save power and die area. An ADC circuit can use redundancy bit(s), e.g., one or more DAC unit elements of a main DAC, and the remaining lower bits of the main DAC for repeated bit trials, and can average the data from the repeated bit trials to suppress noise from conversions.