Shared Track-and-Hold Circuits for Interleaved ADC Calibration
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Solution Overview
Problem
Designing high-speed track and hold (T/H) circuits for analog-to-digital converters (ADCs) is challenging due to issues with power consumption, noise, and performance, particularly in achieving timing and bandwidth matching across multiple channels in time-interleaved ADCs.
Innovation Solution
The implementation of improved T/H circuits that incorporate additive and multiplicative dither signals for calibration, allowing for the linearization of non-linearities and mismatch calibration between ADC slices, while using a single dedicated T/H circuit to drive multiple ADCs, reducing power consumption and eliminating timing and bandwidth mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple separate T/H circuits are used to drive multiple ADCs in time-interleaved configuration, then each ADC channel can be independently optimized, but timing and bandwidth mismatches occur between channels and power consumption increases
Solution Approach 1:
The patent merges multiple T/H circuit functions into a single shared T/H circuit that serves multiple ADCs in a time-interleaved configuration. This single circuit uses time-multiplexed switching to sequentially connect to different ADC channels, eliminating the need for separate T/H circuits per channel. The switching mechanism allows one T/H circuit to replace what would traditionally require multiple independent circuits, thereby reducing power consumption while maintaining timing synchronization across all channels through centralized control.
Solution Approach 2:
The patent implements periodic switching between different ADC channels using a time-interleaved architecture. The single T/H circuit periodically connects to each ADC channel in sequence according to a predetermined timing pattern, allowing each channel to receive serviced at regular intervals. This periodic action ensures that timing and bandwidth characteristics remain consistent across channels while reducing the overall power consumption compared to having continuously active separate circuits for each channel.
2Measurement precision
If dither signals are injected into the T/H circuit, then non-linearities and mismatches can be calibrated, but circuit complexity increases
Solution Approach 1:
The patent introduces dither signals as an intermediary element to facilitate calibration of the T/H circuit. These small-amplitude periodic signals are injected into the circuit to excite non-linearities and mismatches, which then manifest as measurable artifacts in the ADC output. By analyzing these artifacts and applying appropriate correction algorithms, the system can calibrate gain, offset, and timing mismatches without requiring complex hardware modifications. The dither signals act as a simple yet effective mediator that enables precise calibration through software-based correction rather than hardware complexity.
3Use of energy by stationary object
If a single T/H circuit drives multiple ADCs, then power consumption is reduced and timing matching is improved, but the T/H circuit must operate at higher speeds
Solution Approach 1:
The patent employs dynamic switching mechanisms that allow the single T/H circuit to adaptively manage its operating speed and connection timing to multiple ADCs. The circuit uses high-speed switches that can rapidly connect and disconnect from different ADC channels in a time-interleaved fashion. This dynamic operation enables the T/H circuit to maintain high conversion rates by sequentially serving multiple channels, effectively distributing the speed requirement across time rather than requiring all channels to be served simultaneously. The dynamic switching architecture allows the circuit to operate at higher speeds while maintaining power efficiency through time-multiplexed operation.
Data Source
AI summary
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.