Time-Interleaved SAR ADC Control Using Asynchronous Sub-Conversions
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Solution Overview
Problem
ADC circuitry using successive approximation register (SAR) faces challenges in achieving balanced power consumption, speed of operation, and conversion accuracy, particularly due to issues with synchronous sub-conversion operations leading to potential errors and inefficiencies in high-speed conversion processes.
Innovation Solution
The implementation of mixed-signal circuitry with an array of ADC units operating in a time-interleaved manner, where each conversion comprises a sequence of asynchronous sub-conversion operations, and a controller that monitors and controls the circuitry to adjust power consumption, speed, and accuracy by utilizing Conversion Complete signals to manage supply voltage and bulk voltage, allowing for asynchronous operation and dynamic adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If synchronous sub-conversion operations are used in ADC circuitry, then the conversion process is simplified and easier to control, but errors may occur and conversion accuracy deteriorates under high-speed operation
Solution Approach 1:
The patent transitions from synchronous to asynchronous sub-conversion operations, allowing each operation to complete dynamically without being constrained by a fixed clock cycle. This dynamic approach ensures that each sub-conversion operation completes successfully before the next begins, eliminating timing-related errors while maintaining control through completion detection signals.
Solution Approach 2:
The patent introduces completion detection signals that provide feedback on whether each sub-conversion operation has finished successfully. This feedback mechanism allows the system to wait for proper completion of each operation before proceeding to the next, ensuring accuracy without requiring complex synchronous timing control.
2Measurement precision
If more sub-conversion operations are performed to improve accuracy, then conversion accuracy improves, but power consumption increases
Solution Approach 1:
The asynchronous operation mode allows the ADC circuitry to perform the minimum necessary sub-conversion operations dynamically based on actual conversion needs. Each operation proceeds only when the previous one completes, avoiding unnecessary operations and reducing power consumption while maintaining required accuracy.
Solution Approach 2:
The patent changes the operational parameters from fixed synchronous timing to variable asynchronous timing, allowing each sub-conversion operation to take only as long as needed to complete. This parameter change enables the system to achieve required accuracy with fewer or more operations as needed, optimizing power consumption accordingly.
3Productivity
If the number of ADC units in the array is increased to improve conversion speed, then productivity improves, but device complexity increases
Solution Approach 1:
The patent divides the ADC functionality into multiple independent ADC units operating in parallel with time-interleaved operation. Each unit handles a portion of the conversion tasks asynchronously, allowing the system to achieve high conversion speeds through parallel processing while keeping each individual unit relatively simple in structure.
Solution Approach 2:
Each ADC unit in the array operates autonomously with its own completion detection mechanism, performing self-service without requiring complex centralized control. This self-service approach simplifies the overall system architecture by distributing control functions across multiple independent units rather than requiring a complex central controller.
Data Source
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AI summary
Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.