Shared Bootstrapped Sample-and-Hold Circuits for Time-Interleaved ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional time-interleaved analog-to-digital converters (ADCs) face challenges with high gate count, complex clock distribution, and increased silicon area due to the need for multiple switches and capacitances in bootstrapped sample and hold circuits, which complicates calibration and increases power consumption.
Innovation Solution
The proposed solution involves sharing bootstrap capacitance and switches among sample and hold circuits, operating in an overlapping fashion to reduce the number of gates and capacitances required, thereby simplifying clock distribution and reducing calibration needs, with two shared circuits charging and sampling alternately to improve linearity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional bootstrapped sample and hold circuits are used in time-interleaved ADCs, then high resolution and linearity are achieved, but gate count and device complexity increase significantly
Solution Approach 1:
The patent merges the bootstrap capacitance and switch circuits across multiple sample and hold circuits. Specifically, a single bootstrap capacitance is shared among multiple S/H circuits, and a single switch is used to connect this shared capacitance to multiple sampling transistors. This consolidation reduces the total gate count from 8N to 3N+10 while maintaining the bootstrapping function that ensures high linearity and resolution in each S/H circuit.
Solution Approach 2:
The shared bootstrap capacitance and switch circuit serve multiple functions simultaneously: they provide bootstrapping for multiple sampling transistors, reduce circuit complexity, and maintain signal integrity across all N sub-ADCs in the time-interleaved architecture. The single switch structure universally connects the shared capacitance to all required sampling points without requiring separate dedicated circuits for each S/H unit.
2Reliability
If multiple switches and capacitances are used in each sample and hold circuit, then bootstrapping function is maintained, but silicon area increases
Solution Approach 1:
The patent combines multiple separate bootstrap capacitances into a single shared capacitance that serves all sample and hold circuits. Similarly, multiple individual switches are merged into a single shared switch structure. This merging approach maintains the essential bootstrapping function - where the capacitance stores voltage to linearize the sampling transistors - while dramatically reducing the silicon area required for implementing N separate bootstrap circuits.
3Ease of operation
If separate clock distribution is provided for each switch, then switching operation is controlled, but clock distribution complexity increases
Solution Approach 1:
The patent merges the clock distribution architecture by providing a single clock signal that controls the shared switch, rather than requiring N separate clock signals for N individual switches. This single clock distribution approach maintains precise switching control - the shared switch is actuated at the appropriate times to connect the bootstrap capacitance to the required sampling transistors - while eliminating the complex clock distribution network that would be needed to synchronize multiple separate switches.
4Productivity
If more switches are actuated by clock signals, then sampling operation is achieved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by merging multiple actively-switched circuits into a single shared switch structure. Instead of powering N separate switches that are actuated by clock signals, the invention uses one shared switch that is controlled by a single clock signal. This dramatically reduces the total switching activity and associated dynamic power consumption while maintaining the sampling operation - the shared switch efficiently connects the bootstrap capacitance to the appropriate sampling transistors only when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of gates to be driven by clock generation circuitry from 8N to 3*N+10 or 6N to 3*N+2, depending on the availability of a higher power supply, minimizing silicon area and simplifying clock distribution while maintaining high SNDR and linearity.
Implementation Method 1
a first shared circuit operative to charge a first capacitance during one half-period of each period of a master clock signal, and a second shared circuit operative to charge a second capacitance during the other half-period of each period of a master clock signal
Implementation Method 2
The shared (and previously charged) capacitance is placed in series between the input terminal and the gate terminal of a sampling transistor M11, thus improving its linearity
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42) in each of two sets. The two shared circuits (12, 32, 14, 34) alternate, on different half-periods of a master clock signal (Clk), between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit (16, 36, 18, 38, 20, 40, 22, 42) is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals (Clk1-Clk4). To improve SNDR, at least one switch (M11) is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42), the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.