SAR ADC Sequential Conversion for Fewer Clock Cycles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SAR ADCs exhibit low clock utilization and unnecessary power consumption due to treating each sampled signal with a complete conversion process, even when the analog input signal does not significantly change, leading to repeated cycles of sampling and conversion.
Innovation Solution
The SAR ADC employs a sequential A/D conversion method where only the first sampled signal undergoes a complete conversion to determine all bits, and subsequent signals are converted based on the previous digital output signal, reducing the number of clock cycles required for conversion by determining only the changing lower bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complete conversion process is applied to each sampled signal, then conversion accuracy is maintained, but clock utilization decreases and power consumption increases
Solution Approach 1:
The patent applies partial action by performing complete conversion only when necessary (when analog input changes significantly) and partial conversion (only for changed bits) when the input remains stable. The SAR control logic circuit determines whether to execute full or partial conversion based on change detection, thereby optimizing clock utilization while maintaining accuracy when needed.
Solution Approach 2:
The conversion process is made dynamic by allowing it to adapt between full and partial modes based on input signal characteristics. The system dynamically adjusts the conversion depth according to whether the analog input has changed, enabling flexible resource utilization that matches actual processing needs.
2Measurement precision
If a complete conversion process is applied to each sampled signal, then all bits are determined, but power consumption increases due to unnecessary conversions
Solution Approach 1:
The patent implements partial action by performing complete bit determination only when the analog input signal changes. When the input remains stable, only the changed bits are converted, avoiding unnecessary power consumption from redundant conversion operations while maintaining accuracy for the bits that actually need updating.
Solution Approach 2:
The system changes the conversion parameter (conversion depth) based on input signal characteristics. When stability is detected, the conversion parameter is reduced to only the necessary bits, thereby reducing power consumption. When changes are detected, full conversion parameters are restored to ensure accuracy.
3Reliability
If repeated complete conversion cycles are performed, then all bits are consistently determined, but clock utilization decreases
Solution Approach 1:
The patent applies partial action by performing complete conversion cycles only when the analog input signal changes. When the input remains stable, partial conversion is performed only for the changed bits, significantly reducing the number of clock cycles required while maintaining conversion consistency through change-based triggering.
Solution Approach 2:
The system performs preliminary detection of input signal changes before initiating conversion. This preliminary action allows the system to avoid unnecessary complete conversion cycles by identifying stable inputs in advance, thereby reducing clock utilization loss while maintaining reliability through change-based conversion triggering.
Data Source
AI summary
An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.