CMOS Image Sensor ADC Using Half-Ramp Bit Predecision
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Solution Overview
Problem
Conventional CMOS image sensor (CIS) analog-to-digital converters (ADCs) face challenges in reducing power consumption while maintaining high-speed data conversion, as they require increased operation clock frequency to improve resolution, leading to increased power consumption and longer conversion times.
Innovation Solution
The proposed ADC employs a method where one bit is decided through an initial comparison between a half ramp signal and a pixel signal, selecting a rising or falling half ramp signal based on ramping direction, and performs analog-to-digital conversion accordingly, using a ramp signal selector, comparator, and data converter to reduce power consumption and achieve high-speed conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single ADC operates at high speed to convert analog signals from all pixel arrays, then the chip area is reduced, but power consumption increases
Solution Approach 1:
The patent divides the pixel array into multiple groups and assigns different ADCs to process different groups. Each ADC converts analog signals from a specific group of pixel arrays at a lower speed, which reduces power consumption while the coordinated operation of multiple ADCs maintains overall high conversion speed and utilizes chip area efficiently
2Manufacturing precision
If the operation clock frequency of the counter is increased to improve resolution by one bit, then manufacturing precision is improved, but power consumption increases and conversion time increases
Solution Approach 1:
The patent performs preliminary classification of pixel signals into different groups before ADC conversion. By pre-organizing the analog signals from pixel arrays into distinct groups that can be processed by separate ADCs, the system achieves high overall resolution without requiring each individual ADC to operate at extremely high clock frequencies, thus reducing power consumption
3Manufacturing precision
If the operation clock frequency of the counter is increased to improve resolution by one bit, then manufacturing precision is improved, but productivity decreases due to longer conversion time
Solution Approach 1:
The patent segments the pixel array into multiple groups, each processed by a dedicated ADC. This parallel processing architecture enables multiple conversion operations to occur simultaneously, significantly increasing overall conversion speed and productivity while each ADC operates at moderate clock frequencies to maintain required resolution
Data Source
AI summary
An ADC includes: a ramp signal selector suitable for selecting a ramp signal selector suitable for selecting a rising half ramp signal or falling half ramp signal according to a ramping direction detection result from a ramping direction detector; a comparator suitable for outputting an initial comparison result signal by initially comparing a half ramp signal and a pixel signal, and outputting a comparison result signal by comparing the rising or falling half ramp signal selected through the ramp signal selector to the pixel signal; the ramping direction detector suitable for detecting a ramping direction according to the initial comparison result signal from the comparator; and a data converter suitable for deciding an initial bit according to the initial comparison result signal from the comparator, and performing data conversion according to the comparison result signal from the comparator.