Non-Uniform Delay Time-to-Digital Converter for Wide Dynamic Range
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Solution Overview
Problem
Conventional time-to-digital converters require a large number of stages to achieve a high dynamic range, leading to increased area and power consumption, which is inefficient.
Innovation Solution
A time-to-digital converter with N stages of converting circuits, where each stage includes a first delayer and an arbiter, with varying delay times, producing a non-linear binary output to reduce the number of stages and thus area and power consumption, while maintaining dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the quantity of stages of delayers is increased to achieve a large dynamic range, then the dynamic range is improved, but the area and power consumption increase
Solution Approach 1:
The patent changes the delay time parameter of delayers from a uniform value to non-uniform values across different stages. Specifically, delayers in different stages have different delay times, with earlier stages having longer delay times and later stages having shorter delay times. This parameter variation allows the system to achieve a large dynamic range with fewer stages, thereby reducing area while maintaining measurement precision.
2Measurement precision
If the quantity of stages of delayers is increased to achieve a large dynamic range, then the dynamic range is improved, but the power consumption increases
Solution Approach 1:
The patent implements non-uniform delay times across delayer stages, where earlier stages use longer delay times and later stages use shorter delay times. This parameter optimization reduces the total number of delayer stages required to achieve a given dynamic range, thereby directly reducing power consumption while maintaining the same measurement precision.
3Area of stationary object
If the quantity of stages of converting circuits is reduced to decrease area and power consumption, then area and power consumption are reduced, but the non-linearity of output may be affected
Solution Approach 1:
The patent introduces non-uniform delay time parameters across delayer stages to compensate for the reduced number of stages. By carefully designing the delay time distribution (longer delays in early stages, shorter delays in later stages), the system maintains proper non-linearity characteristics and output accuracy while using fewer circuit stages, thus reducing area without sacrificing manufacturing precision.
Data Source
AI summary
A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.