SAR ADC Reference Capacitor Layout for Fast, Calibrated Bit Trials
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive-approximation-register analog-to-digital converters (SAR ADCs) face challenges in achieving fast conversion speed and accurate calibration due to signal-dependent bit weights and the need for external reference capacitors, which introduce errors and impede bit decision speed.
Innovation Solution
The design incorporates on-chip dedicated reference capacitors for each bit capacitor or pair, enabling faster reference settling and signal-independent bit weights, along with a calibration scheme using decide-and-set switching to measure and correct bit weight errors, reducing the need for extensive calibration words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external reference capacitors are used to support instantaneous charge requirements, then the ADC can operate at faster rates, but the speed is impeded by bond wires and external capacitor limitations
Solution Approach 1:
The patent divides the single external reference capacitor into multiple smaller on-chip reference capacitors, each dedicated to specific bit capacitors. This segmentation eliminates the need for external capacitors and bond wires, enabling faster bit decision speeds while maintaining the ability to support instantaneous charge requirements.
Solution Approach 2:
The patent introduces on-chip reference capacitors as intermediaries between the reference voltage source and the bit capacitors. These on-chip capacitors serve as local charge reservoirs that eliminate the speed-limiting bond wires while providing the necessary charge support for fast conversion rates.
2Measurement precision
If calibration algorithms are used to correct non-ideal bit weights, then measurement accuracy improves, but the process becomes complex and requires signal-independent bit weights for easy calibration
Solution Approach 1:
The patent assigns dedicated on-chip reference capacitors to specific bit capacitors, creating local charge reservoirs that ensure signal-independent bit weights. This local quality approach simplifies calibration by making each bit weight independent of signal conditions, allowing for easier measurement and correction of non-ideal bit weights.
3Speed
If on-chip dedicated reference capacitors are used for each bit capacitor, then reference settling speed increases and bit weights become signal-independent, but chip area increases
Solution Approach 1:
Instead of using one large external reference capacitor, the patent segments the reference capacitance into multiple smaller on-chip capacitors distributed across the chip. Each small capacitor is dedicated to specific bit capacitors, achieving fast reference settling locally while minimizing total chip area compared to a single large external capacitor.
4Quantity of substance
If external reference capacitors are used, then charge reservoir capacity is sufficient, but power consumption increases and accuracy is reduced due to bond wire impedances
Solution Approach 1:
The patent introduces on-chip reference capacitors as intermediaries that provide local charge reservoir capacity eliminating the need for external capacitors connected through power-consuming bond wires. These on-chip capacitors maintain sufficient charge reservoir capacity while reducing power consumption and improving accuracy by eliminating bond wire impedances.
Data Source
AI summary
A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).