Shared Track-and-Hold Circuit for Interleaved ADC Calibration
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Solution Overview
Problem
Designing high-speed track and hold (T/H) circuits for analog-to-digital converters (ADCs) is challenging due to issues with power consumption, noise, and performance, particularly in achieving uniform timing and bandwidth across multiple channels in time-interleaved ADCs, where mismatches are difficult to measure and address.
Innovation Solution
The implementation of a single high-speed T/H circuit driving multiple ADC slices, incorporating additive and multiplicative dither signals for calibration to linearize the circuit, calibrate gain and offset mismatches, and reduce power consumption, while using switched-capacitor networks and amplifiers to improve signal-to-noise ratio and variable gain capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate T/H circuits are used for time-interleaved ADCs, then each channel can be independently designed, but timing and bandwidth mismatches occur between channels
Solution Approach 1:
The patent merges multiple T/H circuits into a single shared T/H circuit that serves multiple ADC slices. This is achieved by having one T/H circuit with a sampling network that simultaneously feeds multiple ADC slices, eliminating the need for separate T/H circuits per channel and thereby eliminating timing and bandwidth mismatches between channels.
Solution Approach 2:
The single T/H circuit is designed to perform multiple functions by serving multiple ADC slices. The sampling network within the single T/H circuit is configured to provide sampled signals to multiple ADC slices simultaneously, making the T/H circuit universal and eliminating channel-to-channel variations.
2Manufacturing precision
If a single high-speed T/H circuit drives multiple ADC slices, then timing and bandwidth mismatches are eliminated, but the circuit complexity and power consumption increase
Solution Approach 1:
The single T/H circuit is segmented into multiple functional blocks including a sampling buffer, a sampling network with multiple sampling capacitors, and a hold buffer. Each block performs a specific function, and the segmented architecture allows for modular design and implementation, reducing overall circuit complexity while maintaining uniform timing and bandwidth.
Solution Approach 2:
The patent employs parameter changes by using multiple sampling capacitors with different capacitance values connected to different ADC slices. This allows each ADC slice to receive optimized sampled signals tailored to its specific requirements, reducing circuit complexity while maintaining uniform performance across all channels.
3Device complexity
If traditional T/H circuits are used without dither injection, then the design is simpler, but non-linearities and mismatches are difficult to calibrate
Solution Approach 1:
The patent implements feedback by injecting dither signals into the sampling network and using the resulting calibration data to adjust and correct non-linearities and mismatches in the T/H circuit and ADC slices. This feedback mechanism enables precise calibration of the system, improving measurement precision while managing complexity through systematic calibration procedures.
Solution Approach 2:
The patent applies preliminary action by pre-calibrating the T/H circuit and ADC slices using dither signal injection before normal operation. The calibration process characterizes non-linearities and mismatches in advance, allowing the system to operate with high precision without requiring complex real-time correction circuits.
4Productivity
If high sampling rates are achieved in T/H circuits, then ADC performance improves, but power consumption and noise increase
Solution Approach 1:
The patent employs periodic action by using periodic sampling and holding operations in the T/H circuit. The sampling network periodically samples the input signal at high rates, and the hold buffer periodically updates the sampled values. This periodic operation allows high sampling rates to be achieved while controlling power consumption through efficient switching and capacitor-based storage rather than continuous amplification.
Solution Approach 2:
The patent replaces traditional high-power continuous-time amplification mechanisms with capacitor-based sampling and holding mechanisms. Instead of using high-power amplifiers to maintain signal levels at high sampling rates, the system uses switched-capacitor networks that consume significantly less power while achieving the same high-speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables better performance, lower power consumption, and simplified design by eliminating timing and bandwidth mismatches, improving harmonic performance, and allowing for robust calibration of non-linearities and mismatches, thus enhancing the overall efficiency of high-speed ADCs.
Implementation Method 1
sampling the buffered input signal onto a capacitor
Implementation Method 2
connecting a node having a dither signal to the capacitor to output a held signal
Data Source
AI summary
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.