Integrating Buffer Front-End for Fast Low-Power ADC Settling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving fast settling responses and efficient power consumption, particularly in high-speed applications, due to their exponential settling characteristics and high bandwidth requirements.
Innovation Solution
The implementation of a time-interleaved integrating sampling front-end circuit using integrating buffers, which includes transconductors and resettable capacitors, provides a faster linear settling response and reduces power consumption by more than 30% while maintaining the same footprint, thereby relaxing the required bandwidth by over five times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional exponential settling ADC architecture is used, then the ADC can achieve settling response, but the settling speed is slow and power consumption is high
Solution Approach 1:
The patent changes the fundamental settling characteristic from exponential to linear by using integrating buffers. This parameter change in the settling response type enables both faster settling speed and reduced power consumption, as the linear settling allows for controlled integration over time rather than requiring rapid exponential convergence.
Solution Approach 2:
The patent replaces the conventional voltage buffer mechanism with an integrating buffer mechanism that uses transconductors and capacitors. This substitution fundamentally changes how the settling process occurs, enabling linear settling behavior that is both faster and more energy-efficient than traditional exponential settling approaches.
2Use of energy by moving object
If conventional ADC bandwidth is reduced, then power consumption decreases, but settling response becomes insufficient
Solution Approach 1:
By changing from exponential to linear settling through integrating buffers, the patent decouples the relationship between bandwidth and settling quality. The linear settling characteristic allows precise measurement responses even with lower bandwidth, as the integration process naturally filters and accumulates the signal over the settling period.
3Productivity
If time-interleaved sampling is implemented, then data throughput increases, but circuit complexity increases
Solution Approach 1:
The patent divides the ADC into multiple parallel channels with integrating buffers, where each channel processes samples at lower individual rates. This segmentation allows the overall system to achieve high data throughput through parallel processing while each individual buffer circuit remains relatively simple in structure.
Solution Approach 2:
The integrating buffer circuit serves multiple functions simultaneously: it acts as a buffer, performs integration for linear settling, and enables time-interleaved sampling operation. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing complexity while achieving high throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed ADCs with reduced power consumption and improved data throughput, suitable for applications like Serializer-Deserializer, FPGA I/O, and 5G technologies, by achieving a faster linear settling response and lower bandwidth requirements.
Implementation Method 1
Some embodiments may use integrating buffers to perform integrations and obtain the linear settling response
Data Source
AI summary
Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi≥1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi≥1, at least one buffer of the Xi buffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.