Adaptive ADPLL Bandwidth Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Existing all-digital phase-locked loops (ADPLLs) face challenges in adaptively controlling closed-loop bandwidth based on phase changes within a search window, leading to suboptimal performance in lock state and unlock state transitions.
Innovation Solution
The ADPLL employs a closed-loop bandwidth adjustment circuit that detects phase changes using a search window defined by reference clock signals, comparing feedback signals with a bangbang phase frequency detector to control bandwidth dynamically, and includes a lock detector to determine the lock or unlock state, thereby adjusting the bandwidth accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the closed-loop bandwidth is increased to reduce lock time, then the lock time is reduced, but the power consumption increases and jitter performance deteriorates
Solution Approach 1:
The patent applies dynamics by making the closed-loop bandwidth adjustable rather than fixed. The system dynamically switches between a first closed-loop bandwidth (for fast locking) and a second closed-loop bandwidth (for low power and low jitter) based on the lock state detection. This allows the system to optimize performance at different operational stages, reducing overall power consumption while maintaining fast lock capability when needed.
Solution Approach 2:
The patent changes the bandwidth parameter adaptively based on the lock state. By detecting whether the PLL is in lock or unlock state and相应ly adjusting the closed-loop bandwidth, the system achieves fast acquisition during unlocking while minimizing power consumption and jitter during locked operation. This parameter change strategy resolves the contradiction between fast locking and low power consumption.
2Measurement precision
If the closed-loop bandwidth is increased to improve frequency accuracy, then the frequency accuracy is improved, but the jitter performance worsens
Solution Approach 1:
The system dynamically adjusts the closed-loop bandwidth based on lock state detection. During unlock state, a first closed-loop bandwidth is used to achieve fast frequency acquisition and accuracy. During lock state, a second closed-loop bandwidth is applied to minimize jitter while maintaining adequate frequency accuracy. This dynamic adjustment resolves the contradiction between frequency accuracy and jitter performance.
Solution Approach 2:
The patent changes the closed-loop bandwidth parameter according to operational state. By switching between different bandwidth values based on whether the system is locked or unlocked, the patent achieves high frequency accuracy during acquisition while minimizing jitter during steady-state operation, thereby resolving the trade-off between these two performance metrics.
3Device complexity
If a fixed closed-loop bandwidth is used, then the device complexity is reduced, but the adaptability to different operational states worsens
Solution Approach 1:
The patent introduces dynamic adaptability by implementing a lock state detection mechanism that automatically adjusts the closed-loop bandwidth. The system includes a lock detector that monitors the lock state and controls the bandwidth adjustment circuit to switch between different bandwidth values. This dynamic approach significantly improves adaptability to different operational states while adding minimal complexity through the use of standard PLL components.
Solution Approach 2:
The patent implements feedback by using a lock detector to monitor the PLL lock state and feed this information back to the bandwidth adjustment circuit. This feedback mechanism enables the system to automatically adapt its bandwidth parameter based on the current operational state, improving versatility without requiring complex external control logic. The feedback loop ensures the system responds appropriately to changes in lock state.
Data Source
AI summary
A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window.