Adaptive Block Family Error Avoidance Scan for TLC Memory
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Solution Overview
Problem
Memory sub-systems, such as solid-state drives, face errors due to variations in threshold voltages over time, leading to inaccurate data reading and reduced device lifespan, as manufacturing variances and degradation cause deviations from target voltages, and temperature differences at writing and reading affect different memory levels differently.
Innovation Solution
Implementing a Block Family Error Avoidance (BFEA) scan that adjusts read level voltages by using multiple wordlines to determine different voltage offset values for each page, enhancing read voltage accuracy and reducing bit error rates, thereby extending the memory device's lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single BFEA scan is performed on one page type, then the scan complexity is reduced, but the voltage calibration accuracy is insufficient for other page types
Solution Approach 1:
The patent divides the memory pages into three separate page types (lower page, upper page, extra page) and performs independent BFEA scans for each type. This segmentation allows each page type to have its own optimized read voltage calibration, resolving the contradiction by increasing measurement precision through multiple targeted scans while keeping each individual scan relatively simple.
Solution Approach 2:
The patent applies the BFEA scan methodology universally across all three page types, using the same scanning approach but adapting it to each specific page type's characteristics. This multi-functional application ensures consistent voltage calibration accuracy across different page types without requiring fundamentally different scanning mechanisms.
2Ease of operation
If read voltage is not adjusted for different page types, then the operation is simpler, but bit error rates increase due to voltage shifts
Solution Approach 1:
The patent implements local quality by determining specific read voltage offsets for each page type (lower page, upper page, extra page) based on their individual BFEA scan results. Each page type receives a customized voltage adjustment tailored to its specific characteristics, improving reliability by addressing voltage shifts locally for each page type rather than using a universal adjustment.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on the detected page type and the corresponding BFEA scan results. By adjusting the read voltage offset according to the specific page type being accessed, the system maintains ease of operation through automated parameter selection while significantly improving bit error rates through precise voltage calibration.
3Duration of action of stationary object
If manufacturing variances and degradation are not compensated, then the device lifespan is reduced, but voltage compensation increases operational complexity
Solution Approach 1:
The patent performs preliminary BFEA scans during manufacturing and at initialization to establish baseline read voltage offsets for each page type before the memory device enters normal operation. This preliminary action captures manufacturing variances early and creates compensation parameters that extend device lifespan by pre-correcting for systematic voltage deviations.
Solution Approach 2:
The patent implements feedback by periodically performing BFEA scans to detect voltage shifts caused by degradation over time and temperature effects. The system uses this feedback information to update read voltage offsets dynamically, maintaining accurate voltage calibration throughout the device's operational life and extending lifespan through continuous adaptation to degradation.
Data Source
AI summary
Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.