Static Storage TRIZ Cases

Parallel roll call circuits output test data simultaneously across shared data buses, reducing sequential testing time in semiconductor memory arrays.

A semiconductor memory device uses a data IO control portion to write and read test pattern data across multiple memory regions simultaneously.

A memory apparatus with a signal feeding circuit block enables direct control of the memory circuit to output test patterns for verification.

Etching channel openings through select gate tiers to the conductive tier enables direct electrical coupling with channel material.

Repair comparison circuit detects additional fuse rupture operations by comparing row addresses with generated fuse data.

A test mediation device converts signal frequencies to match memory operations while storing fail addresses.

GOYA tool determines optimal memory instance configuration to maximize good chip dies per wafer.

Built-in self-test unit identifies defective DRAM cells during power-up to prevent performance degradation.

A BFEA scan adjusts read voltages using multiple wordlines to determine distinct offset values for each page type.

A latency measurement circuit calculates roundtrip write-to-read latency using electromagnetic coupling between data paths.

A memory controller uses parity blocks to reconstruct corrupted data from independent media units.

Segmenting memory testing into selective margin checks reduces boot latency by skipping full signal training when stability constraints are met.

A memory sub-system monitors die-level health indices to dynamically modify voltage and frequency parameters.

Segmented ECC tests correct read disturbance errors faster than RAID by utilizing pre-stored redundancy page data for uncorrectable bits.

SRAM buffers log memory commands and addresses internally, bypassing external analyzers that interfere with failure occurrence.

A semiconductor repair circuit uses decoders to store address data in a shared fuse array.

A configurable universal register removes circuit elements from the input-output path to improve setup and output timing performance.

Interleaving multiple data streams into single parity packets reduces transmission time across limited I/O interfaces.

A control circuit adjusts internal supply voltage based on clock frequency to optimize memory device performance.

Stacked DRAM logic die transfers data via through silicon vias to resolve the contradiction between increasing data bandwidth and rising power consumption.

A semiconductor memory cell uses a bent gate electrode overlapping bit lines to reduce unit area.

Segments storage addresses into non-contiguous ranges with gaps to detect aliasing errors caused by incorrect bit usage in 31-bit and 64-bit modes.

An L2 cache stores ECC check bits in byte enable storage locations to protect data against bit errors.

An internal power supply protective element connects to branch lines to provide dedicated discharge paths for surge currents.