Memory At-Speed Test Mechanism via Dynamic Signal Path Reconfiguration
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Solution Overview
Problem
Existing memory apparatus test methods cannot perform an at-speed test on the actual signal transmission path of the output function circuit due to bypassing the memory circuit during scan testing.
Innovation Solution
A memory apparatus with an at-speed test mechanism that includes a memory circuit, an output function circuit block, and a signal feeding circuit block. The signal feeding circuit block comprises a feeding flip-flop circuit, a feeding logic circuit, and a feeding multiplexer, which allows direct control of the memory circuit to output test patterns, enabling an output at-speed test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan test is performed on memory input/output interface, then testing of input function circuit and output function circuit is achieved, but memory circuit is bypassed and at-speed test cannot be performed on actual signal transmission path
Solution Approach 1:
The patent implements dynamic mode switching capability that allows the memory apparatus to transition between scan test mode and at-speed test mode. The test mode control signal dynamically reconfigures the signal transmission path: in scan test mode, the memory circuit is bypassed for comprehensive circuit testing; in at-speed test mode, the memory circuit is included in the signal path to enable actual signal transmission testing. This dynamic reconfiguration resolves the contradiction by allowing both test types to be performed as needed.
Solution Approach 2:
The patent introduces a test mode control signal as an intermediary element that mediates between the scan test requirements and at-speed test requirements. This control signal activates different signal transmission paths through control logic, enabling the system to select whether to include or bypass the memory circuit based on the desired test type. The intermediary control mechanism allows both test methodologies to coexist without conflict.
2Ease of operation
If memory circuit is bypassed during scan test, then input function circuit and output function circuit can be tested, but actual signal transmission path cannot be verified
Solution Approach 1:
The system dynamically reconfigures the signal transmission path based on test mode. During scan test, the memory circuit is bypassed to simplify the testing of input/output function circuits. During at-speed test, the memory circuit is included in the active signal path to verify actual signal transmission. This dynamic path selection resolves the contradiction by adapting the circuit configuration to the specific test requirements.
Solution Approach 2:
The patent segments the testing process into distinct phases: scan test phase for comprehensive circuit functionality verification, and at-speed test phase for signal transmission path verification. By separating these test objectives into distinct operational modes, the system can optimize the signal path for each specific test type, allowing function circuit testing without memory bypass when needed, and at-speed testing with full signal path when needed.
Data Source
AI summary
The present disclosure discloses a memory apparatus having at-speed test mechanism. An output function circuit block receives an output signal from a memory circuit to generate an output result. A signal feeding circuit block includes a feeding flip-flop circuit, a feeding logic circuit and a feeding multiplexer. The feeding flip-flop circuit receives and outputs a feeding signal. The feeding logic circuit receives and processes the feeding signal to generate a processed control signal. The feeding multiplexer is electrically coupled to the feeding flip-flop circuit and the feeding logic circuit. In an at-speed test mode, a test pattern is written to the memory circuit and the feeding multiplexer selects the feeding signal to be a feeding control signal to operate the memory circuit to directly control the memory circuit to output the test pattern in the output signal such that the output result is verified to perform an output at-speed test.