L2 Cache ECC Implementation via Byte Enable Repurposing

Solution Overview

Problem

The existing L2 cache is prone to bit errors that corrupt data, and conventional ECC implementations require additional storage and hardware, making them costly and less attractive.

Innovation Solution

A method is introduced where ECC check bits are generated and stored in the intermediary cache instead of byte enables, allowing data protection without the need for additional storage or complex hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ECC implementations are used to protect data in L2 cache, then data reliability is improved, but device complexity and storage requirements increase

Engineering Contradiction:

Improvedata reliabilityVSAvoidhardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the ECC check bit storage function with the existing byte enable storage structure in the L2 cache. By determining that all bytes in a data word are enabled or coherent, the system stores ECC check bits in the same storage location that would normally hold byte enables, thereby protecting data without requiring additional dedicated storage space or complex hardware structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The storage location in the L2 cache that is universally used for byte enables is made multi-functional by allowing it to store ECC check bits when all bytes are enabled. This universal storage structure serves dual purposes: tracking byte enable status during write operations and providing ECC protection during read operations, eliminating the need for separate dedicated storage for ECC check bits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If conventional ECC implementations are used to protect data in L2 cache, then data reliability is improved, but storage space requirements increase

Engineering Contradiction:

Improvedata reliabilityVSAvoidstorage space

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges the ECC check bit storage function with the existing byte enable storage structure in the L2 cache. By determining that all bytes in a data word are enabled or coherent, the system stores ECC check bits in the same storage location that would normally hold byte enables, thereby protecting data without requiring additional dedicated storage space or complex hardware structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent discards the traditional byte enable storage approach when all bytes are enabled, and recovers the storage space by using it for ECC check bits instead. This space recovery mechanism allows the same physical storage location to serve the ECC function without requiring additional die space or increasing storage capacity requirements.

Inventive Principle:

Principle #34Discarding and recovering

3Ease of operation

If byte enables are stored for each byte in the data word, then write operation control is improved, but storage space is consumed

Engineering Contradiction:

Improvewrite operation controlVSAvoidstorage space

Core Design Contradiction:

Ease of operationVSQuantity of substance

Solution Approach 1:

Instead of storing byte enables for every single byte (excessive action), the system stores a single indicator bit that represents whether all bytes in the data word are enabled or coherent (partial action). This partial storage approach is sufficient for the ECC function, reducing storage space requirements while maintaining the ability to identify when complete word protection is needed.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8099650B1L2 ECC implementation

Publication Date: 2012.01.17 NVIDIA CORP

AI summary

One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.