Semiconductor Memory Device Parallel Test Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices require repetitive high frequency tests to ensure all memory cells operate correctly, leading to longer testing times and higher costs due to the limited number of memory cells that can be tested simultaneously.
Innovation Solution
A semiconductor memory device design that allows simultaneous testing of all memory regions during both low and high frequency tests by using a data IO control portion to write and read test pattern data across all memory regions, with a test control signal generating portion to compare data and generate error detecting signals, enabling conditional output of test status data based on error occurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high frequency memory tests are performed on all memory cells to ensure correct operation, then testing reliability is improved, but testing time increases significantly due to the need for repetitive operations on limited numbers of memory cells simultaneously
Solution Approach 1:
The memory cell array is divided into multiple memory blocks (first memory block, second memory block, etc.), allowing parallel testing of different segments. The test control signal generating portion generates separate error detecting signals for each memory block, enabling simultaneous verification of multiple segments during high frequency testing.
Solution Approach 2:
The patent merges the testing of multiple memory blocks into a single unified test operation. The data IO control portion writes test pattern data to and reads from multiple memory blocks simultaneously, combining what would traditionally require separate repetitive operations into one concurrent testing process.
2Productivity
If the number of memory cells tested simultaneously during high frequency tests is increased, then testing efficiency is improved, but the complexity of the test control system increases
Solution Approach 1:
The data IO control portion is designed to handle multiple memory blocks universally, performing the same write and read operations across different memory blocks without requiring separate dedicated control circuits for each block. This multi-functional design increases testing efficiency while avoiding proportional increases in system complexity.
Solution Approach 2:
The test control signal generating portion automatically generates error detecting signals by comparing read data with expected test pattern data for each memory block. This self-service mechanism eliminates the need for external complex control systems, allowing parallel testing of multiple blocks with minimal additional complexity.
Data Source
AI summary
The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.