Memory Array Etching via Insulator Etch-Stop Tier

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Solution Overview

Problem

Current memory array technologies face challenges in efficiently forming memory cells with precise control over select gate tiers and wordline tiers, which affects the overall performance and reliability of memory arrays.

Innovation Solution

The method involves forming a substrate with a conductive tier, an insulator etch-stop tier, and multiple select gate tiers, followed by etching to create channel openings that extend through the select gate tiers and insulator etch-stop tier to the conductive tier, allowing for the formation of channel material directly coupled with the conductive material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional memory array formation methods are used, then manufacturing process is simpler, but manufacturing precision and control over select gate tiers and wordline tiers deteriorates

Engineering Contradiction:

Improvecontrol over select gate tiers and wordline tiersVSAvoidmemory cell structure formation process

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The memory array formation process is segmented into distinct stages: forming select gate tiers with specific materials, creating insulator tiers, forming wordline tiers, and etching channel openings. Each tier is formed and processed separately, allowing precise control over the structural parameters of select gate tiers and wordline tiers while maintaining manufacturability through systematic process breakdown.

Inventive Principle:

Principle #1Segmentation

2Reliability

If select gate tiers and wordline tiers are formed with precise control, then memory array performance improves, but manufacturing complexity increases

Engineering Contradiction:

Improvememory array performanceVSAvoidformation process of memory cell structures

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The method performs preliminary actions by first forming the conductive tier, then sequentially forming select gate tiers with specific materials, creating insulator tiers, and forming wordline tiers before etching channel openings. This preliminary structuring establishes precise control over select gate tiers and wordline tiers early in the process, ensuring memory array performance while streamlining subsequent manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250159875A1Memory Array and Methods Used in Forming a Memory Array

Publication Date: 2025.05.15 MICRON TECHNOLOGY INC

AI summary

A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.