Configurable Universal Register Timing Optimization
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Solution Overview
Problem
Traditional registers in logic array blocks of configurable integrated circuit dies often increase setup and output timing due to circuit elements along the input-output path, which can adversely affect the performance of these blocks.
Innovation Solution
The design of a configurable universal register that removes circuits from the input-output path while maintaining functionality, featuring a master and slave latch arrangement with feedback loops and a DFT circuit path that is not in series with the registered or combinatorial circuit paths, allowing for improved timing performance through configuration bits and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional registers with circuit elements along the input-output path are used, then functionality is maintained, but setup timing and output timing are increased
Solution Approach 1:
The patent extracts and removes unnecessary circuit elements from the input-output path of the register. Specifically, it eliminates intermediate buffers and logic gates that were traditionally present, directly connecting the data input to the master latch and the slave latch output to the data output. This extraction of harmful circuit elements reduces the timing delay without sacrificing the register's core functionality of data storage and transfer.
2Loss of time
If circuits are removed from the input-output path to improve timing, then setup and output timing are reduced, but functionality may be compromised
Solution Approach 1:
The patent implements feedback loops that connect the slave latch output back to the master latch input and include control signal paths that feed back to configure the register's operation mode. These feedback paths ensure that the register maintains proper state management and operational control even with the simplified input-output structure, thereby preserving functionality while achieving timing improvements.
Solution Approach 2:
The patent designs a universal register structure that can operate in multiple modes (transparent latch mode, registered mode, and bypass mode) through configuration bits. This multi-functionality ensures that the simplified register structure can still perform various functions required by different logic array block configurations, maintaining reliability while achieving timing improvements.
3Loss of time
If a simplified register structure is used to improve timing, then setup and output timing are reduced, but adaptability to different configurations may be limited
Solution Approach 1:
The patent employs dynamic configuration through control signals and configuration bits that allow the register to change its operating mode on-the-fly. The register can be dynamically switched between transparent latch mode, registered mode, and bypass mode based on the logic array block's requirements. This dynamic adaptability ensures that the simplified register structure can serve multiple configuration needs without compromising timing performance.
Data Source
AI summary
An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.