Test Mediation Device for Memory Yield and Repair
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Solution Overview
Problem
Current test devices for memory devices are limited in their ability to perform repair processes in package or module states, as they lack the necessary storage for repair information, leading to potential misclassification of repairable devices as failed and reduced yield and increased test time.
Innovation Solution
A test mediation device that stores repair information and supplies high-level voltage for cutting fuses, enabling repair processes in package or module states by converting test information frequencies and storing fail addresses in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test conditions are toughly set in wafer state to prevent fail in package or module state, then reliability of test is improved, but yield of memory devices decreases
Solution Approach 1:
The patent performs preliminary testing in wafer state with standard test conditions, then conducts additional testing in package/module state. This staged approach allows preliminary identification of obvious failures without prematurely rejecting devices that might pass final testing, thereby maintaining both test reliability and yield.
Solution Approach 2:
The patent introduces an intermediary testing stage in package or module state between wafer-level testing and final product acceptance. This intermediary stage uses appropriate test conditions for the specific state, acting as a bridge that prevents both over-rejection and under-detection of failures.
2Device complexity
If test device does not store repair information, then device complexity is reduced, but ease of repair deteriorates
Solution Approach 1:
The patent extracts the repair information storage function from the test device itself and places it in external storage media or separate systems. This allows the test device to remain simple while still enabling comprehensive repair processes through external information storage and retrieval.
Solution Approach 2:
The patent creates copies of repair information in external storage systems rather than requiring the test device to store all repair data. This allows the test device to remain simple while external systems maintain comprehensive repair information for later use in repair processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables stable repair processes, increases memory device yield, and reduces test time and costs by facilitating repair operations in previously unsupported states.
Implementation Method 1
A test mediation device for coupling a memory device operating at a first frequency and a test device operating at a second frequency
Implementation Method 2
store the address corresponding to the fail memory cells as a fail address
Implementation Method 3
a redundancy circuit includes a metallic fuse for storing fail information on a memory device, for example, the address of a fail memory cell, word line, or bit line, and the fuse is cut using a laser
Implementation Method 4
A redundancy circuit for repairing a fail memory device may include an electrical fuse, for example, e-fuse, that is electrically cut in order to overcome a limit resulting from a metallic fuse that is cut by a laser
Data Source
AI summary
A system for testing a memory device includes a memory device configured to include a plurality of memory cells, receive a test information having a first frequency, access memory cells corresponding to an address included in the test information, and activate a fail signal if fail occurs in the memory cells corresponding to the address, a test device configured to generate a test information having a second frequency different from the first frequency, and a test mediation device configured to generate the test information having the first frequency and the address based on the test information having the second frequency and the fall signal and store the address corresponding to the fail memory cells in response to the fail signal as a fail address.