Multi-Phase ECC Memory Controller Error Recovery
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Solution Overview
Problem
Memory systems face errors due to changes in cell threshold voltage caused by read disturbance and data retention, leading to failed bits in data reading outputs, which existing error correction methods struggle to effectively address.
Innovation Solution
A memory system with a memory controller that performs multi-phase Error-Correcting Code (ECC) tests, using both first and second phase ECC data stored within and separately from data pages, respectively, to correct errors, and optionally employs RAID technology for further protection, allowing for faster and more efficient error recovery compared to traditional ECC schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-phase ECC methods are used, then the error correction process is simple, but the error correction capability is insufficient for severe errors caused by read disturbance and data retention
Solution Approach 1:
The ECC correction process is divided into two distinct phases: first-phase ECC correction using ECC data stored in the same page as the data, and second-phase ECC correction using ECC data stored in a separate redundancy page. This segmentation allows the system to handle different error scenarios with appropriate correction methods, improving overall error correction capability while maintaining manageable complexity through structured processing
2Reliability
If RAID-based error correction methods are used, then the error correction capability is enhanced, but the data recovery time is increased
Solution Approach 1:
ECC data is pre-calculated and stored in two locations before errors occur: first-phase ECC data is stored in the same page with the data, and second-phase ECC data is stored in a redundancy page. When errors are detected, the system can immediately attempt correction using the pre-prepared first-phase ECC data, and only if that fails does it proceed to the second-phase correction, significantly reducing recovery time compared to RAID methods that require reading multiple pages
3Reliability
If only first-phase ECC data stored in the data page is used, then the storage structure is simple, but the error correction capability is insufficient for uncorrectable errors
Solution Approach 1:
A redundancy page is introduced as an intermediary storage structure that holds second-phase ECC data. This redundancy page acts as a mediator between the data page and the error correction process, providing additional correction capability for errors that cannot be corrected by the first-phase ECC data alone, while maintaining a clear separation between data storage and error correction functionality
Data Source
AI summary
Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.