Bent Gate Electrode for Semiconductor Memory Cell Area Reduction
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Solution Overview
Problem
As semiconductor memory devices integrate, the complexity of manufacturing vertical channel MOS transistors increases, leading to poor contact between metal bit lines and drain, and the short channel effect becomes challenging to avoid due to adjacent gate electrode interference.
Innovation Solution
A semiconductor integrated circuit device design featuring parallel word and bit lines with gate electrodes that are bent to overlap with bit lines, sharing word lines and bit lines between adjacent memory cells to reduce area and alleviate the short channel effect, while using bit line contacts positioned away from crossing points to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical channel MOS transistor is adopted to reduce memory cell area, then area efficiency is improved, but manufacturing process complexity increases and contact quality deteriorates
Solution Approach 1:
Instead of forming a vertical pillar structure with surrounding gate electrode, the patent inverts the approach by forming a horizontal gate electrode that extends to overlap with the bit line. This inverted structure achieves similar area efficiency without the manufacturing complexity of vertical pillar formation and surrounding etching processes.
Solution Approach 2:
The patent extracts the essential function of the vertical channel device (area efficiency) while removing the problematic vertical pillar structure. The gate electrode is designed to extend horizontally and overlap with the bit line, achieving the desired area reduction without requiring complex vertical formation processes.
2Area of stationary object
If vertical channel MOS transistor is adopted, then area efficiency is improved, but contact quality between metal bit line and drain deteriorates
Solution Approach 1:
Instead of forming a vertical pillar structure with surrounding gate electrode, the patent inverts the approach by forming a horizontal gate electrode that extends to overlap with the bit line. This inverted structure achieves similar area efficiency without the manufacturing complexity of vertical pillar formation and surrounding etching processes.
3Device complexity
If conventional planar structure is used to simplify manufacturing, then manufacturing complexity is reduced, but channel length is insufficient and short channel effect occurs
Solution Approach 1:
The patent extends the gate electrode in the vertical dimension to overlap with the bit line, effectively increasing the channel length without increasing the planar footprint. This dimensional extension allows sufficient channel length to be achieved while maintaining simple planar manufacturing processes.
Solution Approach 2:
The gate electrode is designed with a bent or curved shape that extends vertically to overlap with the bit line. This curved configuration increases the effective channel length while maintaining compatibility with standard planar fabrication processes.
4Length of moving object
If gate electrode is extended to increase channel length, then channel length is improved, but adjacent gate electrodes interfere with each other
Solution Approach 1:
The gate electrode is designed with non-uniform dimensions: it has a first dimension (horizontal width) and a second dimension (vertical extension for overlap). This local variation in dimensions allows sufficient channel length through vertical overlap while controlling horizontal spacing to prevent interference between adjacent gate electrodes.
Solution Approach 2:
The gate electrode is designed with a bent or curved shape that extends vertically to overlap with the bit line. This curved configuration increases the effective channel length while maintaining compatibility with standard planar fabrication processes.
Data Source
AI summary
A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cell regions with each cell region bounded by an adjacent pair of the word lines and an adjacent pair of the bit lines; and gate electrodes for the respective unit memory cell regions, each gate electrode electrically connected with any one of a pair of word lines which delimit a corresponding unit memory cell, and formed such that at least a portion of the gate electrode is bent toward a bit line direction.