Chip Data Verification via Interleaved Parity Encoding
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Solution Overview
Problem
The limited data bandwidth and number of data transmissions in network topology within chips lead to inefficiencies in data exchange between processing circuits, resulting in prolonged data transmission times, especially when multiple data need to be transmitted simultaneously.
Innovation Solution
A data compression mechanism using error detection and correction codes, such as CRC, Hamming codes, and Reed-Solomon codes, is implemented to encode and combine data, allowing multiple data transmissions through a single parity data, reducing the amount of data transmitted and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If network topology is used to reduce cabling cost, then device complexity is reduced, but data transmission time increases due to limited bandwidth and data length
Solution Approach 1:
The patent combines multiple data packets into a single transmitted data stream using interleaving technology. Multiple processing circuits transmit their data simultaneously through shared I/O interfaces by interleaving their data packets in time slots, effectively merging multiple transmission channels into one while maintaining data integrity and reducing total transmission time.
Solution Approach 2:
The patent implements dynamic data transmission by allowing processing circuits to transmit data in alternating time slots through the same I/O interface. The system dynamically allocates transmission opportunities to different processing circuits based on their data readiness, enabling flexible and efficient use of limited bandwidth resources.
2Device complexity
If limited I/O interfaces are used, then device complexity is reduced, but productivity decreases due to insufficient data transmission capacity
Solution Approach 1:
The patent makes each I/O interface universal by enabling it to serve multiple processing circuits through time-division multiplexing. Each I/O interface can dynamically connect to different processing circuits at different time slots, allowing a single interface to perform multiple transmission functions and effectively increasing the system's overall data transmission capacity without adding more physical interfaces.
Solution Approach 2:
The system dynamically reconfigures the connectivity between processing circuits and I/O interfaces in real-time. Processing circuits can be dynamically assigned to different I/O interfaces based on data priority, buffer status, and interface availability, maximizing the utilization of limited I/O resources and maintaining high productivity.
3Productivity
If multiple data are transmitted simultaneously through network topology, then productivity is improved, but data transmission time increases due to bandwidth limitations
Solution Approach 1:
The patent segments data transmission into smaller packets that can be interleaved and transmitted in alternating time slots. By dividing the data stream into manageable packets and transmitting them in an interleaved manner across multiple time slots, the system achieves efficient use of bandwidth while maintaining high throughput and reducing overall transmission time.
Solution Approach 2:
The patent implements periodic data transmission by alternating between different processing circuits in regular time slots. Each processing circuit transmits its data packets periodically when its turn comes, creating a rhythmic and predictable transmission pattern that optimizes bandwidth utilization and ensures fair access to the shared I/O interfaces.
Data Source
AI summary
A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.