Memory Instance Configuration for Yield Optimization
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Solution Overview
Problem
Current methods for designing integrated circuits with embedded memory systems face challenges in yield optimization, particularly for System-on-Chip (SoC) designs with hundreds of memory cores, as they restrict themselves to Poisson distribution and do not effectively determine the optimal configuration of memory types and sizes with or without redundant elements to achieve the highest possible yield.
Innovation Solution
An electronic design tool, such as the General and Optimal Yield Analyzer (GOYA), determines the optimal configuration of memory instances with and without built-in repair capacity to maximize the number of good chip dies per wafer by calculating the threshold-values for each memory instance, balancing yield increase with area occupation, and selecting the appropriate number of repairable and non-repairable memory instances based on defect density and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory instances with built-in repair capacity are increased, then yield is improved, but die area occupation increases
Solution Approach 1:
The patent changes the parameter of repair capacity configuration by calculating threshold-values for each memory instance based on defect density and area, determining the optimal mix of repairable and non-repairable memories to maximize yield per wafer while controlling area usage
Solution Approach 2:
The patent applies local quality by assigning different repair capacities to different memory instances based on their individual characteristics (area, defect density), rather than uniformly configuring all memories with the same repair capacity
2Productivity
If the number of memory instances with repair components is increased, then good chip dies per wafer is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into repairable and non-repairable portions, with only necessary memory instances equipped with repair components (spare rows/columns, repair logic), reducing overall complexity while maintaining productivity
Solution Approach 2:
The patent applies partial action by providing repair capacity to only those memory instances that benefit most from it, rather than equipping all memory instances with full repair capabilities
Data Source
AI summary
A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.