Adaptive Common-Mode Buffer Biasing for Low-Rate ADC Power Scaling
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Solution Overview
Problem
Analog to digital converters (ADCs) face inefficiencies in power consumption, as the power consumption of the common mode buffer does not scale linearly with conversion rate, limiting flexibility and increasing complexity when trying to reduce power at lower conversion rates.
Innovation Solution
An adaptive biasing system that generates a variable bias current, which changes magnitude based on sampling activity, using a current mirror circuit and a parallel transistor circuit to adjust the bias current in response to the conversion rate, reducing power consumption by adjusting the common mode voltage generation accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a bias circuit generates multiple discrete bias currents using programming bits, then power consumption can be reduced at lower conversion rates, but device complexity increases due to additional circuitry for generating and altering programming bits
Solution Approach 1:
The patent implements dynamic bias current adjustment by continuously varying the bias current magnitude based on the actual conversion rate of the ADC, rather than using fixed discrete levels. The bias circuit monitors the conversion rate and automatically adjusts the bias current to match the operational demands, eliminating the need for complex programming bit circuitry while achieving power savings.
Solution Approach 2:
The patent employs feedback mechanisms where the bias circuit receives information about the actual conversion rate from the ADC operation and uses this feedback to adjust the bias current accordingly. This closed-loop approach allows the system to automatically optimize power consumption without requiring external programming or complex control logic.
2Use of energy by moving object
If a bias circuit uses programming bits to generate multiple discrete bias currents, then power consumption can be adjusted, but adaptability is limited to specific conversion rates
Solution Approach 1:
The patent transitions from static discrete bias levels to dynamic continuous adjustment. The bias circuit continuously adapts the bias current magnitude to match any conversion rate within the operational range, providing full adaptability rather than being constrained to specific predetermined rates.
Solution Approach 2:
The patent changes the bias current parameter dynamically based on the conversion rate. Instead of selecting from fixed discrete levels using programming bits, the system continuously varies the bias current magnitude to precisely match the operational requirements at any given conversion rate.
3Stability of the object's composition
If the common mode buffer operates at fixed bias current, then it provides stable common mode voltage, but power consumption does not scale with conversion rate
Solution Approach 1:
The patent makes the common mode buffer's bias current dynamic rather than fixed. The buffer continuously adjusts its bias current based on the conversion rate while maintaining stable common mode voltage output through feedback control, allowing power consumption to scale with actual operational demands.
Solution Approach 2:
The patent changes the bias current parameter of the common mode buffer dynamically according to conversion rate requirements. The buffer maintains voltage stability through control mechanisms while allowing the current parameter to vary, achieving both stability and energy efficiency.
Data Source
AI summary
A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.