Power Saving Provisions TRIZ Cases

A time-multiplexed shared amplifier cuts ADC chip area and power use while preserving high-speed, high-resolution flash conversion.

Selective clock tracking gates inactive DAC latches to cut power use while preserving synchronized unit-cell switching and analog accuracy.

A bidirectional VCO and dual-converter ADC enables direct RF or IF sampling with fewer channels, lower power use, and reduced interleaving spurs.

Upper-bound-guided SAR ADC skipping cuts mixed-signal MAC power use while preserving accurate digital outputs for vector multiplication.

A voltage-to-time inter-stage converter lets a hybrid ADC keep high sample rates while cutting power and improving PVT robustness.

Dual comparators switch between coarse and fine counting clocks to speed image-sensor ADC conversion while cutting power use.

Feedforward current-source toggling in a current-steering DAC cuts power during low code ranges while preserving SNR before signal spikes.

Multiple actuating electrodes and digital mapping linearize optical DAC modulation, improving dynamic range and signal quality.

Cascaded delay and logic stages generate multiple internal clocks from a lower-frequency input, cutting ADC clock complexity and power.

A tree of selectively clocked comparators cuts ADC power and kickback noise while preserving fast conversion for IoT and biomedical use.

Using a calibration DAC at a rational fraction of the ADC rate separates alias components digitally, easing anti-alias filter area and loss.

Progressively enabled DAC elements cut thermal noise and power in digital microphone sigma-delta ADCs while preserving stability.

Regulated level shifters and added bias current let current-steering DACs extend output swing while keeping switches saturated for better linearity.

A micro-coded sequencer lets ADC and CTMU peripherals run and process data without CPU control, cutting power use in sleep modes.

Switched parallel capacitors and phase detection replace custom high-power inductors, keeping load voltage and current near phase alignment.

Receiver ADC and equalization logic cut valid-bit processing on low-loss channels, reducing power while preserving signal reliability.

Timed enable signals let analog measurement and threshold checking run without CPU supervision, cutting power use and bandwidth load.

A VCO-based time-domain integrator enables a low-order two-step CDC architecture that delivers fine capacitance resolution with low conversion energy.

A time-encoding audio detector flags voice activity with low power draw, reducing wake-up delay and preventing speech data loss.

Using double data rate comparator cores, floating references, and an inverted clock, this flash ADC cuts kickback noise and power use.

A shared gain-control capacitor lets the SAR ADC buffer amplify samples and receive residue feedback, improving accuracy without extra area or power.

A dynamic amplifier and switched-capacitor path shape SAR ADC noise while cutting static current, die area, and input-referred noise.

Matching unit-cell impedance in active and sleep states cuts charge injection, lowers EVM, and improves RFDAC transmitter linearity.

Variable bias current tracks ADC sampling activity, cutting common-mode buffer power at low conversion rates without added programming logic.

Reusing prior SA quantizer codes when sample changes stay below a threshold cuts digital microphone power without unnecessary code searches.

A sample-and-hold circuit lets the ADC run intermittently, cutting sensor-interface power while preserving signal accuracy across temperature changes.

Digital calibration lets open-loop ADC amplifiers cut analog power and complexity while preserving inter-stage gain accuracy and linearity.

An ADC reuses its conversion capacitor scheme to generate DSP power, cutting PMIC loss, area, heat, and voltage fluctuation in low-noise sensors.

A NAND-plus-inverter delay chain detects long comparator decisions in self-clocked SAR ADCs to prevent wasted toggling and save power.

Mapped binary actuation across segmented electrodes overcomes Mach-Zehnder nonlinearity to improve optical DAC dynamic range.

An ASIC stays quiet between photon, particle, or ion hits, then records only event data to cut power, memory use, and transfer load.

A timer, data hold register, and calculation circuit generate analog waveforms without DMA, cutting memory use, bandwidth load, and power.

A low-resolution ADC monitors signal changes and triggers high-resolution conversion only when needed, cutting power use and bandwidth waste.

A two-stage ADC combines fast first-stage conversion with delta-sigma residue processing to improve accuracy without high power or slow speed.

A three-stage voltage-current-time pipeline converts ADC residue into time, boosting speed and power efficiency while preserving resolution.

A noise-shaping filter lets a SAR ADC raise effective resolution while reducing comparator power and area demands.

Multiple independently driven electrodes linearize optical DAC output, improving dynamic range while limiting Mach-Zehnder distortion.

Variable-capacitance cells with distinct threshold voltages convert analog input into binary signals compatible with capacitive adiabatic logic.

Delayed counter start removes offset-voltage counts in image sensor ADC readout, cutting wasted power in dark conditions.

Grouped DAC electrodes cut bottom-plate parasitic capacitance in GHz time-interleaved SAR ADCs, improving speed and power efficiency.

A timer-based ADC control scheme selects the lowest sleep mode that still meets wake-up and conversion timing for accurate low-bandwidth sampling.

A shared bandpass NS-SAR ADC handles non-contiguous aggregated carriers in one receiver path, cutting RF power and chip area.

A differential delay line enables bipolar time measurement without TDC offset, cutting power and phase noise while preserving timing precision.

Repurposing MAC output capacitors as CDAC elements enables shared ADC conversion in compute-in-memory arrays, saving die space and easing data movement.

Variable bias current scaling lets an ADC common mode buffer cut power at lower conversion rates without added discrete control complexity.

Switched-capacitor internal attenuation lets a SAR ADC handle high input signals with lower latency and power for industrial motor control.

A nulling monitor circuit isolates amplifier distortion from the fundamental signal, enabling lower-power ADCs and better echo cancellation.

Shared OTA and cascode switching keep a pipeline ADC ready between sampling phases, cutting RADAR converter power without losing settling time.

A shared impedance string lets one DAC generate multiple output resolutions while cutting switch count, leakage current, power use, and circuit area.

A current-steering feedback loop balances opposite input currents in an ADC to cut DAC power use and input-level dependence in imaging.