ADC Counter Start Timing for Low-Power Image Sensor Readout
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Solution Overview
Problem
High power consumption in image sensors due to the need for counters to account for offset voltages in analog to digital conversion processes, particularly in dark conditions where the dynamic range is low, leading to significant energy wastage.
Innovation Solution
Implementing a delayed counter start time to eliminate counts caused by offset voltages, synchronizing the ramp reference and image signals, and using dividers or flip-flops to achieve this delay, thereby reducing power consumption without affecting the readout data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the counter starts counting from the beginning of the ramp signal to ensure accurate analog to digital conversion, then the conversion accuracy is maintained, but the power consumption increases significantly due to unnecessary counts caused by offset voltages
Solution Approach 1:
The patent applies preliminary action by delaying the counter start time to occur after the offset voltage has settled, rather than starting immediately with the ramp signal. This is achieved by using a delay circuit that postpones the counter enable signal, allowing the initial offset voltage transient to decay before counting begins. The conversion accuracy is maintained because the delay is precisely controlled to match the offset settling time, while power consumption is reduced by eliminating unnecessary early counts.
Solution Approach 2:
The patent changes the timing parameter of the counter operation by introducing a variable delay period. The counter start time is shifted relative to the ramp signal based on the offset voltage characteristics. This parameter adjustment allows the system to adapt to different offset conditions while maintaining conversion accuracy, and significantly reduces power consumption by minimizing the number of counter operations required.
2Adaptability or versatility
If the counter operates continuously to handle all ramp signal variations, then all signal conditions are covered, but power is wasted in dark conditions where dynamic range is low
Solution Approach 1:
The patent applies partial action by having the counter operate only for the necessary duration after the offset voltage settles, rather than continuously throughout the entire ramp cycle. The counter is enabled selectively based on the actual signal conditions, performing only the minimum required counting operations. This maintains adaptability to handle all signal conditions while eliminating energy wastage in dark conditions where full-range counting is unnecessary.
Solution Approach 2:
The patent implements periodic action through the use of a delayed counter enable signal that activates only during relevant conversion periods. The counter operates in discrete enabled periods rather than continuously, synchronized with the ramp signal after the offset delay. This periodic operation maintains versatility in handling different signal conditions while significantly reducing energy consumption by keeping the counter inactive during unnecessary periods.
Data Source
AI summary
An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.