Grouped DAC Capacitors for GHz Time-Interleaved SAR ADCs

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Solution Overview

Problem

High-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) face challenges in power efficiency and speed due to significant parasitic capacitance in digital-to-analog converters (DACs), particularly at GHz frequencies, where the DAC load requires multiple stages in the drive chain, increasing power and delay, and the bottom-plate parasitic capacitance has a substantial impact.

Innovation Solution

The solution involves a modified DAC design with grouped capacitance electrodes, reducing parasitic capacitances by scaling capacitance non-linearly and using a dual-path bootstrapped switch to decouple the signal path from nonlinear parasitic capacitance, along with constant-matching scaling and quantized sub-radix-2 capacitor scaling to achieve high speed and power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the DAC capacitance and bottom-plate capacitance are reduced to improve power efficiency and speed, then power consumption and delay decrease, but matching precision and capacitance stability deteriorate

Engineering Contradiction:

Improvepower consumptionVSAvoidcapacitance matching precision

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The bottom-plate capacitance is segmented into multiple smaller capacitances (Cbtm1, Cbtm2, etc.) that are distributed across different bits. This segmentation allows the total capacitance to be reduced while maintaining matching precision through careful distribution and grouping of the segmented capacitance elements throughout the DAC structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different bottom-plate capacitance values are assigned to different bit positions based on their specific requirements. The capacitance distribution is optimized locally for each bit group, with higher-order bits having different capacitance characteristics than lower-order bits, thereby achieving overall matching precision while minimizing total power consumption.

Inventive Principle:

Principle #3Local quality

2Speed

If the drive chain is extended with more stages to improve drive strength for high-speed operation, then speed increases, but power consumption and delay increase

Engineering Contradiction:

Improveoperating speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The drive chain is designed with dynamic sizing where driver strength varies by bit position. More significant bits (MSBs) have stronger drive capability while less significant bits (LSBs) have weaker drive capability. This dynamic allocation of drive strength allows the system to achieve high-speed operation with reduced total power consumption compared to uniform drive sizing.

Inventive Principle:

Principle #15Dynamics

3Measurement precision

If the DAC load is increased to improve resolution, then measurement precision improves, but the number of drive chain stages and power consumption increase

Engineering Contradiction:

Improveconversion resolutionVSAvoiddrive chain complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The DAC capacitance is segmented and distributed across multiple bottom-plate capacitances rather than using a single large capacitance. This segmentation reduces the instantaneous load on any single driver stage while maintaining the total capacitance required for the desired resolution, thereby reducing drive chain complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The capacitance distribution is arranged in a multi-dimensional layout where bottom-plate capacitances are distributed spatially across different bit groups. This spatial distribution allows the DAC to achieve high resolution without concentrating the full capacitive load at a single point, reducing the complexity of the drive chain.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a threefold reduction in bottom-plate parasitic capacitance, improving power efficiency and speed, achieving an SNDR of 36.9 dB at 10 GHz with 21 mW consumption and a figure-of-merit of 37 fJ/conv.-step, outperforming state-of-the-art ADCs in terms of power efficiency and speed.

Implementation Method 1

the total capacitance including both the DAC capacitance and its associated bottom-plate capacitance shown as C(DAC) and Cbtm in FIG. 1, has a significant impact on both the speed and power consumption of the overall converter

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

using a dual-path bootstrapped switch to decouple the signal path from nonlinear parasitic capacitance

Methodology Applied

Scientific EffectBootstrapping:

Data Source

PatentUS11101814B2Time-interleaved successive approximation register analog to digital converter with grouped digital to analog capacitors

Publication Date: 2021.08.24 BRIGHAM YOUNG UNIV

AI summary

The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies.