SAR ADC Stall Detection Delay Chain for Low-Power Clocking
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Solution Overview
Problem
In battery-connected sensor readout systems with long lifetimes, achieving ultra-low power dissipation is crucial, but the high-speed clock required by SAR ADCs for n-bit digital output word resolution conflicts with the need for a low-frequency system clock, and the comparator's long decision time can lead to incomplete conversions before new samples are required.
Innovation Solution
A self-clocked SAR ADC sensor circuit with a stall detection circuit that uses a delay chain with low-power dissipation inverters and a NAND gate to detect and manage long decision times, allowing for efficient clock management and power conservation by preventing unnecessary toggling of the flip-flop and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed clock is used in the ring oscillator to enable the comparator to make decisions within the clock period, then the conversion speed is improved, but the power dissipation increases significantly
Solution Approach 1:
The ring oscillator is configured to dynamically adjust its operating frequency based on the comparator's decision time. The oscillator frequency is matched to the comparator speed, allowing the system to operate at the minimum necessary frequency rather than a fixed high frequency, thereby reducing power dissipation while ensuring conversions complete within available time
Solution Approach 2:
The system changes the operating parameters of the ring oscillator to match the comparator's decision characteristics. By adjusting the oscillator frequency to align with the comparator's actual decision time, the system achieves optimal power efficiency without sacrificing conversion completeness
2Use of energy by moving object
If the system clock frequency is reduced to 10-100Hz for ultra-low power dissipation in battery-connected systems, then power consumption is reduced, but the SAR ADC cannot complete n-bit conversions within the sampling interval
Solution Approach 1:
The ring oscillator frequency is dynamically matched to the comparator decision time rather than being fixed at a low system clock frequency. This allows the ADC to complete conversions efficiently at higher effective speeds while the overall system maintains low average power consumption through selective operation
Solution Approach 2:
The ring oscillator generates clock cycles in advance to ensure the comparator has sufficient time to complete its decision process before the next sampling interval begins, preventing stalled conversions while maintaining low overall power consumption
3Measurement precision
If the comparator decision time is increased to improve accuracy, then measurement precision is improved, but the conversion cannot be completed before a new sample is required
Solution Approach 1:
The stall detection circuit provides feedback about comparator decision status to control the reset timing. When the comparator fails to decide within the expected time, the feedback mechanism adjusts the reset signal timing to prevent premature resets, ensuring accurate comparisons complete while maintaining conversion throughput
Data Source
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AI summary
A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscillator and stall detection. The delay element circuit includes a delay block with a NAND gate followed by a plurality of inverters.