Compute-in-Memory ADC Using Shared CDAC-MAC Capacitors
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Solution Overview
Problem
Compute-in-memory architectures face limitations in processing speed due to the data-movement bottleneck in machine learning applications, particularly because conventional analog-to-digital converters (ADCs) require substantial die space, limiting density and efficiency.
Innovation Solution
Integration of capacitive digital-to-analog converters (CDAC) within compute-in-memory bitcells, where output capacitors function as both MAC circuit output capacitors and CDAC capacitors, allowing for simultaneous multiplication and digitization, thereby reducing the need for separate ADCs and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional separate ADCs are used in compute-in-memory architectures, then conversion accuracy is maintained, but die space increases and density decreases
Solution Approach 1:
The patent merges the ADC functionality with the compute-in-memory bitcell structure by integrating capacitive digital-to-analog converters (CDAC) within the bitcells. The output capacitors of the MAC circuits are repurposed to function as both MAC circuit output capacitors and CDAC capacitors, eliminating the need for separate ADC circuits and reducing die space while maintaining conversion accuracy
Solution Approach 2:
The output capacitors in the bitcells are designed to serve dual functions: acting as output capacitors for the multiply-and-accumulate (MAC) circuit during calculation phases and as CDAC capacitors during digitization phases. This multi-functionality allows the same hardware components to perform multiple roles, reducing the overall die space required
2Speed
If separate ADC circuits are implemented, then conversion functionality is provided, but processing speed is limited due to data-movement bottleneck
Solution Approach 1:
The patent combines the computation and conversion functions into a single integrated structure where the MAC circuit and ADC share common capacitive elements. This integration eliminates the need for separate data movement between distinct computation and conversion units, thereby increasing processing speed and reducing the data-movement bottleneck
Solution Approach 2:
The integrated design allows the system to maintain continuous operation by eliminating idle data transfer phases between separate computation and conversion units. The same capacitive structures are continuously utilized for both computation and digitization without requiring data to be moved between separate circuits, enabling uninterrupted processing
3Device complexity
If conventional ADCs are used, then digitization is achieved, but the number of required ADCs increases system complexity
Solution Approach 1:
Each bitcell's output capacitors are designed to function as both MAC output capacitors and CDAC capacitors, allowing the same hardware to perform both computation and digitization. This eliminates the need for separate ADC circuits for each bitcell, reducing system complexity while maintaining digitization efficiency
Solution Approach 2:
The bitcells are designed to perform their own digitization function using their internal output capacitors as CDAC capacitors. Each bitcell essentially digitizes its own output without requiring external ADC resources, reducing the overall number of ADCs needed in the system
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing speed and density by repurposing output capacitors as CDAC capacitors, simplifying ADC implementation and reducing the number of required ADCs, thus overcoming the limitations of conventional ADCs in compute-in-memory architectures.
Implementation Method 1
an output capacitor having a first plate connected to the first output node and the second output node and having a second plate connected to the read bit line
Data Source
AI summary
A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.