Double Data Rate Flash ADC Quantizer With Reduced Kickback Noise
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Solution Overview
Problem
Modern mobile communication devices require energy-efficient wide bandwidth analog to digital converters (ADCs) that minimize kickback noise for accurate signal conversion, while reducing power consumption and complexity.
Innovation Solution
The proposed solution involves a flash ADC architecture with double data rate comparator cores operating on both clock edges, utilizing floating voltage references and switched capacitor networks to reduce kickback noise and eliminate the need for preamplifiers, thereby lowering power consumption and area complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If preamplifiers are inserted before each comparator to prevent kickback noise, then kickback noise distortion is reduced, but power consumption increases and battery life is reduced
Solution Approach 1:
The patent removes the preamplifier stage from the comparator structure, extracting the harmful power consumption element while maintaining kickback noise protection through alternative means (differential input structure and timing synchronization)
Solution Approach 2:
The patent replaces the analog preamplifier mechanism with a digital timing-based solution using double data rate sampling and synchronous resetting, substituting a power-intensive analog component with a more efficient digital approach
2Measurement precision
If preamplifiers are inserted before each comparator to prevent kickback noise, then kickback noise distortion is reduced, but device complexity and area increase
Solution Approach 1:
The patent extracts and removes the preamplifier component from the ADC architecture, reducing device complexity and area while maintaining accuracy through the double data rate comparator design
Solution Approach 2:
The patent combines the functions of preamplification and kickback noise protection into the differential input structure and timing synchronization mechanism, merging multiple functions into a more integrated design that reduces overall complexity
3Use of energy by moving object
If floating voltage sources are used to reduce power consumption, then power consumption is reduced, but kickback transients are not isolated and input signal distortion increases
Solution Approach 1:
The patent introduces double data rate sampling and synchronous resetting as intermediary mechanisms that mediate between the floating voltage sources and the comparators, isolating kickback transients while maintaining the power efficiency of floating sources
Solution Approach 2:
The patent uses periodic resetting of the differential input signals synchronized with the clock edges, creating periodic action that prevents kickback transient accumulation while maintaining low power operation with floating voltage sources
4Productivity
If double data rate comparator cores are used to process both clock edges, then conversion speed is improved, but kickback noise generation increases
Solution Approach 1:
The patent converts the harmful kickback noise generated by double data rate comparators into a manageable signal by using synchronous resetting that predicts and cancels the noise pattern, transforming the harmful effect into a controllable parameter
Solution Approach 2:
The patent implements feedback through synchronous resetting where the expected kickback noise pattern is predicted based on clock timing and used to pre-condition the differential inputs, creating a feedback mechanism that cancels the harmful noise
Data Source
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AI summary
A flash ADC includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.