SAR ADC Skip Logic for Energy-Efficient Mixed-Signal MACs
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Solution Overview
Problem
Analog-to-digital conversion energy consumption is a limiting factor in mixed signal circuit designs, particularly in neural network workloads where matrix multiplications dominate the computations, leading to high power consumption.
Innovation Solution
Implementing a mixed signal multiply-accumulate (MS-MAC) circuitry that performs digital multiplication and analog accumulation, with skip logic to skip certain successive approximation analog-to-digital conversion steps based on predicted upper bounds of the multiplication results, reducing unnecessary computations and energy usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If successive approximation analog-to-digital conversion is performed completely for all multiplication results, then digital output accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing successive approximation register (SAR) ADC conversion only for the necessary number of bits determined by the upper bound, rather than always performing the complete conversion process. When the upper bound indicates that fewer bits are sufficient to represent the multiplication result accurately, the ADC skips unnecessary conversion steps, thereby reducing power consumption while maintaining the required digital output accuracy.
Solution Approach 2:
The patent uses preliminary action by calculating the upper bound of the multiplication result before performing the ADC conversion. This upper bound calculation is performed in advance to determine the minimum number of bits required for accurate representation, allowing the system to configure the ADC operation beforehand and avoid unnecessary power consumption during the conversion process.
2Use of energy by moving object
If the number of successive approximation analog-to-digital conversion steps is reduced, then power consumption decreases, but computational accuracy may be compromised
Solution Approach 1:
The patent employs feedback by using the calculated upper bound information to dynamically adjust the number of ADC conversion steps. The upper bound calculation provides feedback about the expected magnitude of the multiplication result, which is then used to configure the SAR ADC to perform only the necessary number of conversion steps, ensuring that accuracy is maintained while power consumption is optimized.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the conversion precision parameter of the SAR ADC based on the upper bound calculation. Instead of using a fixed number of conversion steps, the system changes the conversion parameter adaptively - reducing the number of steps when the upper bound indicates lower precision is sufficient, and maintaining full precision when needed, thus balancing power consumption and accuracy.
Data Source
AI summary
An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.