SAR ADC Internal Attenuation for Low-Latency High-Input Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving low latency while maintaining low power dissipation, particularly in industrial motor control applications where high amplitude signals require large devices, leading to increased latency and power consumption.
Innovation Solution
Implementing a Successive Approximation Register (SAR) ADC with internal signal attenuation using switched capacitors to increase the signal-to-noise ratio, allowing higher clock frequencies and smaller latency, and utilizing thin gate transistors to handle high input signals without damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large, thick oxide devices are used to handle large input signals, then the ADC can process high amplitude signals without damage, but the conversion speed becomes slow and latency increases
Solution Approach 1:
The patent employs dynamic switching of capacitor configurations during the conversion process. The capacitor array can be reconfigured between sampling and conversion phases, allowing the same hardware to handle both high-voltage sampling and precise low-voltage conversion, thereby achieving fast conversion speed without sacrificing signal handling capability
Solution Approach 2:
The patent changes the operating voltage parameters dynamically. During sampling, the full-scale high voltage is applied to capture large signals. During conversion, the voltage range is reduced through capacitor switching, enabling fast conversion with thin-oxide devices while maintaining the ability to handle high-amplitude input signals
2Loss of time
If clock frequency is increased to reduce latency, then the ADC output speed increases, but power consumption increases and thin gate devices cannot handle large input signals
Solution Approach 1:
The patent uses periodic switching of capacitor configurations synchronized with the clock signal. During the sampling phase, capacitors are connected to capture the input signal. During the conversion phase, capacitors are reconfigured for precise measurement. This periodic action allows the use of higher clock frequencies without continuous high power consumption, as devices are actively switching only during required phases
Solution Approach 2:
The dynamic reconfiguration of the capacitor array allows the system to adapt its impedance and voltage handling characteristics to match the current operational phase, enabling high-speed operation during conversion while maintaining low power consumption during sampling, thus resolving the contradiction between speed and power
3Speed
If smaller geometry technologies are used to provide faster output, then the ADC conversion speed increases, but the device cannot handle large input signals without stress or damage
Solution Approach 1:
The capacitor array serves as an intermediary between the high-voltage input signal and the sensitive thin-oxide conversion circuitry. During sampling, capacitors are connected to the input to capture high-voltage signals. During conversion, capacitors are switched to isolate the thin-oxide devices from high voltage while maintaining the captured signal for precise measurement, thus protecting sensitive devices while enabling fast conversion
Solution Approach 2:
The patent segments the conversion process into distinct phases (sampling and conversion) with different voltage requirements. The capacitor array is divided into groups that can be independently switched, allowing the system to handle high-voltage sampling in one configuration and precise low-voltage conversion in another, thereby enabling fast output with small geometry devices while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-latency and low-power dissipation analog-to-digital conversion, allowing motor control systems to quickly respond to stimuli, suitable for industrial and battery-powered devices, with reduced thermal noise and compact architecture.
Implementation Method 1
A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed
Implementation Method 2
utilizing thin gate transistors to handle high input signals without damage
Data Source
AI summary
Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.