Successive Approximation Tree ADC for Low-Power Fast Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly flash ADCs, face challenges with high power consumption and significant kickback noise, which are not compatible with wearable and implantable applications, and existing solutions do not adequately address these issues.
Innovation Solution
A Successive Approximation Tree (SAT) ADC topology is introduced, utilizing dynamic StrongARM latch comparators with modified differential transistors and a tree-like configuration, where only one comparator receives a clock signal, and each comparator has two outputs connected to different comparators in the next level, allowing for a single reference voltage and reduced power consumption and kickback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash ADC topology is used to achieve fast conversion speed, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The flash ADC comparator stack is segmented into a tree structure with multiple levels and branches. Instead of having all comparators operate simultaneously, the tree structure enables hierarchical comparison where comparators at different levels are activated sequentially based on previous comparison results, reducing the number of comparators that need to operate at full power simultaneously.
Solution Approach 2:
The patent implements dynamic comparator activation where only necessary comparators are enabled based on previous comparison outcomes. The dynamic element matching (DEM) technique is used to dynamically switch between different comparator configurations, optimizing power consumption while maintaining conversion speed performance.
2Use of energy by moving object
If dynamic comparators are used to reduce energy consumption, then power consumption is reduced, but kickback noise increases significantly
Solution Approach 1:
The patent introduces an intermediary regenerative stage between the initial comparison and final decision. This regenerative stage acts as a mediator that amplifies and cleans up the comparison signal before it reaches the final decision logic, thereby reducing kickback noise while maintaining the energy efficiency of dynamic comparators.
Solution Approach 2:
Different regions of the comparator tree are designed with different qualities. Comparators closer to the root of the tree use fully regenerative structures for low noise, while leaf comparators use simpler dynamic structures for low power. This local differentiation optimizes the trade-off between power consumption and kickback noise generation.
3Ease of manufacture
If resistor reference ladder is used in flash ADC, then reference voltage generation is simplified, but power consumption increases due to static current
Solution Approach 1:
The patent extracts and removes the power-consuming resistor reference ladder from the system. Instead, reference voltages are generated dynamically using current mirrors and transistor-based voltage references that consume significantly less static current while providing the necessary reference levels for the comparator tree.
Solution Approach 2:
The passive resistor-based reference ladder is replaced with an active transistor-based reference system. Current mirrors and regulated current sources substitute for the resistive divider, providing reference voltages with minimal static power consumption while maintaining the required precision.
4Use of energy by moving object
If SAR ADC topology is used to reduce power consumption, then power consumption is reduced, but conversion speed decreases
Solution Approach 1:
The patent merges the advantages of flash ADC (parallel comparison structure) with SAR ADC (sequential approximation logic) by implementing a comparator tree with hierarchical levels. This hybrid structure enables faster conversion than traditional SAR ADC while consuming less power than flash ADC by selectively activating comparators based on previous comparison results.
Data Source
AI summary
An analog-to-digital circuit that digitizes an analog voltage. The analog-to-digital circuit includes plural comparators functionally connected to form a tree that has levels i, and each level i has branches j, and an encoder connected to the plural comparators and configured to generate a digitized value of an input analog voltage. Each comparator from a level i has first and second outputs, and each of the first and second outputs is electrically connected to an input of different comparators from a next level i+1 of the tree.