ADC Internal Timer for Low-Power Sampling Accuracy
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in accurately sampling low bandwidth signals due to the time required to exit a low power mode, which can affect conversion accuracy and efficiency.
Innovation Solution
The implementation of a circuit with a timer that determines and accounts for the power up time when transitioning between low power modes, ensuring that the ADC is ready for the next conversion cycle within the sampling time, by converting power up times into clock periods and selecting the lowest power mode that meets this requirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the ADC enters a low power mode between conversion cycles, then power consumption is reduced, but the time required to exit the low power mode increases and may affect conversion accuracy
Solution Approach 1:
The patent applies preliminary action by calculating and storing the power up time for each low power mode in advance, before the ADC actually transitions between modes. The timer is pre-configured with the appropriate power up time value based on which low power mode will be entered, allowing the system to predict and plan for the wake-up time needed for accurate conversion.
Solution Approach 2:
The patent implements dynamics by making the timer configuration adaptive and variable rather than fixed. The timer value is dynamically selected based on the specific low power mode that will be entered, allowing the system to optimize between different power consumption levels and their corresponding power up times. This dynamic adjustment resolves the contradiction by matching the timer setting to the actual power mode transition requirements.
2Loss of energy
If the ADC enters a low power mode to reduce power consumption, then energy efficiency is improved, but the sampling time available for the next conversion is reduced
Solution Approach 1:
The patent applies preliminary action by calculating the power up time in advance for each low power mode option. This pre-calculation allows the system to determine beforehand whether entering a low power mode will leave sufficient sampling time for the next conversion, preventing situations where power savings compromise conversion accuracy.
Solution Approach 2:
The patent implements feedback by using the timer to monitor and ensure that the power up time plus conversion time does not exceed the sampling time. The system continuously checks whether the ADC can complete its power up and conversion within the available sampling window, providing feedback that guides whether to enter or remain in low power modes.
3Loss of energy
If multiple low power modes are available for the ADC, then power consumption can be optimized, but the complexity of managing different power up times increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the power up time for each available low power mode before the ADC operates. This pre-computation simplifies runtime decision-making, as the system only needs to retrieve pre-determined power up time values rather than calculating them dynamically, reducing the complexity of managing multiple power modes.
Solution Approach 2:
The patent implements self-service by enabling the ADC to automatically select and manage its own power mode transitions based on the pre-calculated power up times. The timer and control logic work together autonomously to determine when to enter or exit low power modes without requiring complex external management, allowing the ADC to self-optimize its power consumption while handling multiple modes.
Data Source
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AI summary
An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.