Dual-Clock ADC Circuit for Fast Low-Power Image Sensing
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Solution Overview
Problem
Current analog-to-digital conversion technologies, such as single slope ADCs, face challenges in meeting the demands of high resolution and high speed imaging while maintaining low power consumption, especially as image resolution increases.
Innovation Solution
The proposed analog-to-digital conversion circuit employs a dual-clock system with a first clock signal of lower frequency for coarse counting and a second clock signal of higher frequency for fine counting, controlled by comparators and a counter circuit that enables counting only when the signal levels between the analog and ramp signals meet specific conditions, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single slope ADC is used to meet small pixel size requirements, then device complexity is reduced, but conversion speed becomes insufficient for high speed imaging
Solution Approach 1:
The patent divides the conversion process into two stages: a first conversion stage using a single slope ADC for coarse conversion, and a second conversion stage using a differential ADC for fine conversion. This segmentation allows each stage to use optimized circuit architectures, achieving both low complexity and high speed performance.
Solution Approach 2:
The patent dynamically switches between different conversion modes based on signal conditions. The dual-clock system enables adaptive operation where the first counter operates at a lower frequency for power efficiency during coarse conversion, and the second counter operates at a higher frequency for speed during fine conversion.
2Measurement precision
If single slope ADC is used for high resolution conversion, then measurement precision is improved, but power consumption increases due to counter requirements
Solution Approach 1:
The patent segments the counting operation into two phases: a first counting phase using a first counter with lower power consumption for coarse quantization, and a second counting phase using a second counter with higher precision for fine quantization. This reduces overall power consumption while maintaining high resolution.
Solution Approach 2:
The patent changes the operational parameters of the counters dynamically. The first counter operates with a first clock signal at lower frequency for power efficiency, while the second counter operates with a second clock signal at higher frequency for precision. The system adapts parameters based on conversion stage requirements.
3Productivity
If conversion speed is increased to meet high speed imaging requirements, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic action by implementing dual-clock systems where the first counter operates at a lower frequency periodically for coarse conversion, and the second counter operates at a higher frequency periodically for fine conversion. This periodic switching optimizes the balance between speed and power consumption.
Solution Approach 2:
The patent dynamically adjusts operating frequencies based on conversion requirements. During coarse conversion phases, lower frequencies reduce power consumption. During fine conversion phases, higher frequencies increase speed. The system adapts its dynamic characteristics to match instantaneous performance requirements.
Data Source
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AI summary
An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal.