ADC Calibration DAC Rational Sampling for Anti-Alias Relief
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Solution Overview
Problem
The calibration of multi-channel transceiver chip ADCs is hindered by the need for sharp anti-alias filters, which are difficult to implement on-chip due to silicon area and loss constraints, especially when operating at different sampling rates, leading to limitations in post-calibration accuracy and increased complexity.
Innovation Solution
A calibration DAC samples at a rational fraction of the ADC sampling frequency, allowing digital processing to distinguish between aliased spectral components and signal components, thereby relaxing the anti-alias filter requirements and eliminating the need for sharp on-chip filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a calibration DAC samples at the same frequency as the ADC, then calibration can be performed, but sharp anti-alias filters are required which increase silicon area and loss
Solution Approach 1:
The patent changes the sampling frequency parameter of the calibration DAC from matching the ADC frequency to being a rational fraction (p/q) of it. This parameter change allows aliased spectral components to fall at predictable, distinguishable frequencies, eliminating the need for sharp anti-alias filters and reducing silicon area requirements.
2Object-affected harmful factors
If high-order on-chip LC-filters are used for anti-aliasing, then spectral image suppression is improved, but silicon area and loss increase significantly
Solution Approach 1:
The patent extracts the anti-alias filtering function from the analog domain to the digital domain. By sampling at a rational fraction frequency, the aliased images are pushed to predictable frequencies where they can be removed by simple digital filtering, eliminating the need for complex analog LC-filters and their associated silicon area.
3Object-affected harmful factors
If the calibration DAC operates at integer multiple of ADC sampling frequency, then spectral images are pushed out, but the DAC requires higher sampling rate capability
Solution Approach 1:
Instead of increasing the DAC sampling rate to push images out (conventional approach), the patent inverts the approach by reducing the DAC sampling rate to a rational fraction of the ADC rate. This causes images to fold back to predictable, low-frequency locations where they can be easily identified and removed digitally.
4Adaptability or versatility
If multiple filters with RF-multiplexing are used for different sampling rates, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal calibration approach where the rational fraction sampling method works for any ADC sampling rate. The same calibration DAC and digital processing architecture can be used across different operating conditions, eliminating the need for multiple filters and RF-multiplexing components.
Data Source
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AI summary
An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.