Hybrid ADC Residue Conversion for High-Speed Low-Power Quantization
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) face challenges in achieving high-speed and low-power performance, particularly in deep submicron CMOS technology, where voltage domain amplifiers require high power consumption and are sensitive to process-voltage-temperature (PVT) variations, limiting their suitability for high-resolution designs.
Innovation Solution
A hybrid ADC architecture that employs a first converter stage for voltage domain quantization and a second stage for time domain quantization, with an inter-stage converter that converts residual voltage from the voltage domain to the time domain, allowing for simultaneous operation and reducing power consumption while maintaining linearity and robustness against PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage domain amplifiers are used in deep submicron CMOS technology, then conversion rate can be achieved, but power consumption increases and sensitivity to PVT variations worsens
Solution Approach 1:
The patent replaces voltage domain amplifiers with a time domain quantizer that operates on voltage residues without requiring high-gain amplification. The time domain quantizer converts voltage residues to time intervals, eliminating the need for power-hungry voltage amplifiers in deep submicron CMOS technology while maintaining high conversion rates.
Solution Approach 2:
The patent transforms the quantization domain from voltage to time, changing the fundamental parameter being quantized. This parameter transformation allows the system to achieve high conversion rates without requiring high-gain voltage amplifiers, thereby reducing power consumption and PVT sensitivity in advanced CMOS processes.
2Speed
If voltage domain amplifiers are used to achieve high conversion rate, then speed improves, but stability against PVT variations deteriorates
Solution Approach 1:
The patent substitutes voltage domain amplification with time domain quantization, replacing a PVT-sensitive mechanism with a more robust time-based measurement approach. The time domain quantizer measures voltage residues as time intervals, which are less sensitive to PVT variations than voltage amplification chains.
3Measurement precision
If pipeline architecture with inter-stage amplifiers is used, then medium-to-high resolution is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the traditional pipeline architecture with inter-stage voltage amplifiers with a hybrid architecture where the second stage is a time domain quantizer. This substitution eliminates the need for power-consuming inter-stage amplifiers while maintaining the ability to achieve medium-to-high resolution through time domain measurement.
4Speed
If flash ADC topology is used, then conversion rate is high, but hardware complexity increases exponentially with resolution
Solution Approach 1:
The patent segments the ADC into two distinct stages: a first stage that handles coarse quantization and a second stage implemented as a time domain quantizer for fine quantization. This segmentation allows the system to achieve high conversion rates without requiring the exponential hardware complexity of a full flash ADC, as the time domain quantizer provides high resolution with linear rather than exponential scaling.
Data Source
AI summary
An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.