Adaptive Buffer Circuit for Stable Cross-Clock Data Transfer
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Solution Overview
Problem
Data signals transmitted between different clock domains in digital circuit systems are prone to metastable states, leading to voltage and current ripples due to sudden interruptions in circuit operations.
Innovation Solution
A buffer circuit with a memory circuit and control circuit that adjusts the frequency of write and read clock signals based on the remaining data volume to prevent voltage and current ripples by managing data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buffer circuit suddenly interrupts data transmission when memory space is full, then data loss is prevented, but voltage ripples and current ripples are caused due to drastic power changes
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The control circuit dynamically changes the write clock frequency based on the remaining memory space, transitioning from a static interruption approach to a dynamic frequency modulation approach that prevents both data loss and power fluctuations
Solution Approach 2:
The patent changes the frequency parameter of the write clock signal based on the remaining data volume in the memory circuit. When remaining space is sufficient, normal frequency is used; when space is limited, the frequency is reduced to prevent overflow, thereby avoiding sudden interruptions and the associated voltage/current ripples
2Productivity
If the buffer circuit continuously transmits data at high speed, then productivity is improved, but data loss occurs when memory space is exceeded
Solution Approach 1:
The patent implements feedback by having the control circuit continuously monitor the remaining data volume in the memory circuit and use this information to adjust the write clock frequency. This closed-loop control ensures that transmission speed is automatically reduced when memory space becomes limited, preventing data loss while maximizing throughput when space is available
Data Source
AI summary
A buffer circuit including a memory circuit and a control circuit is provided. The memory circuit stores an input data from a data transmitting device, and transmits an output data to a data receiving device. The control circuit computes a remaining data volume of the memory circuit, and generates a control signal according to the remaining data volume. The remaining data volume represents a volume of data to be transmitted which are stored in the memory circuit. The control signal controls the data transmitting device to generate a write clock signal, and the control circuit reduces a frequency of the write clock signal by the control signal when the remaining data volume increases.