Digital Storage TRIZ Cases

A self-tuning delay circuit tracks cross-domain timing shifts to keep sense signals aligned and prevent premature sensing in memory circuits.

Conditional flop-core activation keeps only active shift-register stages running, cutting driver power use without disrupting data transmission.

Bias-controlled pull-up and pull-down paths let semiconductor memory outputs vary slew rate and timing without changing circuit structure.

Multiple SPI pins transmit address and data bits concurrently, cutting clock cycles and speeding random reads in serial flash memory.

Rewritable truth tables and dual readout decoders let memory cell blocks operate as logic circuits without rewiring while enabling data feedback.

An SNM detector pulls the SRAM word line toward ground during vulnerable writes, improving noise margin and reducing data corruption.

A test-row compare checks power stability before flash-to-SRAM loading, preventing corrupt configuration data at startup.

Triplicated FPGA configuration control with a watchdog detects SEFIs and triggers reconfiguration to maintain operation in radiation-tolerant devices.

Multiple programmable linear receiver stages reshape DQS timing to align skewed DQ signals and create a stable DDR sampling window.

Staggered clock delays in dual current-passing units cut flip-flop output delay while preserving input sensitivity and reducing errors.

Location-based adjustable drive lets memory sense amplifiers cut excess current, lower power use, and preserve access speed.

A shared strobe-delay circuit keeps DRAM column path control signals aligned under PVT variation, preventing read/write timing errors.

A bootstrapped word line driver uses HV isolation and MOS gating to keep fast reads at low supply voltage while improving program inhibit and leakage.

Bias-voltage control keeps memory delay time stable across process, voltage, and temperature shifts, preserving sensing margin within tRCD.

Independent small clock buffer control preserves clock pulse timing in memory power-down and self-refresh modes, preventing missed pulses.

Variable delay units and current control tune delay variation to match PVT conditions, improving jitter across a wider synchronizing circuit frequency band.

Using constant-current charge and discharge above MOS threshold voltage, this case stabilizes DRAM refresh timing despite temperature variation.

Dedicated SPI access to non-volatile PLD memory preserves user data during reconfiguration and enables flexible shadow flash storage.

Interleaving half-cells increases redundant node spacing, preserving SEU tolerance and data integrity in scaled CMOS memory arrays.

Transfer gates equalize differential input-node capacitance and timing, suppressing noise-induced errors during high-speed signal comparison.

Body bias voltages adjust sense amplifier flip-flop offset without extra capacitors, larger layout, or fuse cutting.

A delayed write leveling circuit aligns DRAM clock and data strobe edges to improve write accuracy while reducing power use and jitter.

Dynamic output drive strength lets a multi-die flash package report die status on a shared bus without contention or extra status commands.

Bias ramping in memristive crossbar arrays cuts leakage-related ambiguity and supports continuous switching across more than 100 states.

Delay calibration aligns HBM check-pin data levels with sampling pulses to reduce parity sampling errors under PVT variation and crosstalk.

Different protective materials on gate sidewalls help small DRAM gate stacks resist etching damage while preserving transistor characteristics.

Offset cancellation and pre-sensing balance complementary DRAM bit-line charge, improving sense amplifier sensitivity during restore.

Clock frequency is adjusted to buffer fill level, preventing overflow, metastability-related interruptions, and power ripples during data transfer.

A digital detector replaces bulky ADCs by integrating bit line current and counting thresholds for faster, smaller in-memory computation.

By combining reference and storage functions in one magnetoresistance element, this case improves array density without sacrificing read reliability.

Sequential boost and supply voltages let a bitline sense amplifier restore memory cell data accurately and set bit lines to target levels.

Smoother antiferromagnet-contact interfaces boost spin current injection, enabling magnetic order reversal and stronger memory readout signals.

Segmented SRAM sub-arrays switch between single-row reads and parallel digital compute mode to improve throughput without analog bit-flip risk.

Delta-sigma neuron feedback enables in-memory memristive training with lower data movement, better accuracy, and tolerance to synapse variability.

ECC error signals and scrub addresses identify hammered DRAM rows so only adjacent victim rows are refreshed, preserving data with lower power overhead.

A thermal gradient and injected current write stable voltage-based logic states, reusing on-chip heat for fast superconducting memory.

Phase-change resistive memory uses tunable programming pulses to hold data briefly, then revert automatically for secure, low-energy deletion.

A timer-based skip circuit avoids unnecessary DRAM self-refresh during brief entry-exit intervals, cutting logic errors and power use.

Different interconnect heights between MRAM and logic regions cut chip area and power use while preserving MTJ sensing and data retention.

A dual-voltage latch node lets a memory sense amplifier transfer data between circuits without a separate level shifter, cutting power use.

Reference-voltage sensing reads series MTJ multi-bit MRAM cells without complex resistance measurement, enabling denser memory arrays.

A current-limiting transistor stabilizes MRAM read current to preserve voltage difference, reduce read errors, and prevent cell disturbance.

Alternating reads across cache bitcell banks cut SRAM latency to two cycles while lowering leakage-driven power consumption.

A step voltage pulse turns on threshold selectors before sensing, limiting snapback current and preserving programmable memory cell state.

By combining domain-wall detection with magnetization-state matching, this case improves magnetic memory read accuracy and usable storage capacity.

Vertical oxide bonding places CMOS control circuitry above the memory array to shrink footprint while supporting faster switching and lower power.

Placing sense amplifiers at column edges and wordline drivers in the center cuts wiring load and speeds DRAM core operation.

A control circuit stores defect mappings and switches hierarchical bit lines to redundant cells, preserving data integrity in 3D memory.

Crossbar memory cells, selectors, and adders cut data transfer and power use while preserving real-imaginary correlation in vector neural MACs.

A clock-switched address generator keeps same-bank DRAM refresh addresses aligned row by row, improving refresh efficiency and reliability.