HBM Check Pin Sampling Delay Calibration for Read Signal Alignment
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Solution Overview
Problem
High bandwidth memory (HBM) read data signals are prone to errors due to chip process, operating voltage, and crosstalk, leading to inaccurate parity check signals and sampling errors in traditional detection methods.
Innovation Solution
A processing method involving time-shifting data signals through delay circuits to align level values with sampling pulse signals, determining delay parameters, and adjusting sampling delays to improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read data signal is transmitted together with a parity check signal and a sampling pulse signal for traditional detection, then the receiver can sample the parity check signal based on the sampling pulse signal to check whether the read data signal is transmitted incorrectly, but the parity check signal and the sampling pulse signal may deviate due to chip process, operating voltage, ambient temperature, and crosstalk between signals, causing sampling errors and erroneous check information
Solution Approach 1:
The patent applies preliminary action by performing delay parameter calibration before actual data transmission. The system pre-determines the delay parameters of the parity check signal and sampling pulse signal under different PVT conditions, storing these calibrated values for future use. This preliminary calibration ensures that when actual transmission occurs, the signals are already optimized for accurate sampling, preventing sampling errors caused by PVT deviations.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting delay parameters based on PVT conditions. The system measures actual PVT values during operation and selects or adjusts delay parameters accordingly. This allows the timing characteristics of the parity check signal and sampling pulse signal to adapt to changing environmental conditions, maintaining sampling accuracy despite variations in temperature, voltage, and process.
2Device complexity
If the parity check signal and sampling pulse signal are transmitted without delay adjustment, then the transmission process is simple, but sampling errors occur due to signal deviation caused by chip process, operating voltage, and temperature variations
Solution Approach 1:
The system performs preliminary delay parameter calibration by transmitting calibration signals and measuring their arrival times under different PVT conditions. These pre-determined delay parameters are stored in a lookup table or calibration data structure. During actual operation, the system only needs to retrieve and apply the appropriate delay parameter based on current PVT conditions, avoiding complex real-time adjustments while maintaining high sampling accuracy.
Solution Approach 2:
The system implements self-service through automatic delay parameter selection and adjustment. The controller automatically measures PVT conditions, selects the appropriate delay parameter from pre-calibrated data, and adjusts the signal timing without requiring manual intervention or complex external calibration equipment. This self-adjusting mechanism maintains sampling accuracy while keeping the overall system structure relatively simple.
3Measurement precision
If delay parameters are calibrated for each PVT condition, then sampling accuracy is maintained under varying conditions, but the calibration process and device complexity increase
Solution Approach 1:
The system manages calibration complexity by organizing delay parameters as functions of PVT conditions. Instead of treating each calibration as a separate complex process, the system creates a structured parameter set where delay values are indexed by temperature, voltage, and process conditions. This parameterization approach allows efficient storage and retrieval of calibration data, reducing the complexity of managing multiple calibration scenarios while maintaining high sampling accuracy across all conditions.
Data Source
AI summary
This application relates to a processing method for configuring a check pin of a memory performed by a computer device. The method includes: receiving a first data signal and a sampling pulse signal returned by a check pin in a target memory; time-shifting each first data signal through a delay circuit to align a target level value in each first data signal after the time shift with the sampling pulse signal to obtain a first delay parameter; and when receiving a second data signal returned by the check pin in the target memory, time-shifting a target data signal in each second data signal through the delay circuit to align target level values in all second data signals after the time shift to obtain a second delay parameter, determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.